公开(公告)号：US08390560B2

公开(公告)日：2013-03-05

申请号：US12968953

申请日：2010-12-15

申请人： Yoshihiko Toyoshima ,  Seiichiro Jinta

发明人： Yoshihiko Toyoshima ,  Seiichiro Jinta

IPC分类号： G09G3/36

CPC分类号： H03K19/018557 ,  G09G3/3266 ,  G09G3/3611 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286

摘要： A level shift circuit includes: a first and a second output transistor outputting voltages derived from a first and a second power source voltage, respectively; a first and a second input transistor outputting, based on a first input pulse signal, a first voltage for turning ON the first output transistor and a second voltage for turning OFF the second output transistor, respectively; a third and a fourth input transistor outputting, based on a second input pulse signal, a third voltage for turning OFF the first output transistor and a fourth voltage for turning ON the second output transistor, respectively; a first bootstrap circuit enlarging an amplitude of the first voltage and supplying the same to the first output transistor; and a first voltage compensation circuit, based on a third input pulse signal, making, at an end timing of the first input pulse signal, a voltage change in a direction opposite to that of a voltage fluctuation caused in the first voltage due to a parasitic capacitance in the first input transistor.

摘要翻译： 电平移位电路包括：分别从第一和第二电源电压输出电压的第一和第二输出晶体管; 第一和第二输入晶体管，分别基于第一输入脉冲信号输出用于接通第一输出晶体管的第一电压和用于关断第二输出晶体管的第二电压; 第三输入晶体管和第四输入晶体管，分别基于第二输入脉冲信号输出用于使所述第一输出晶体管截止的第三电压和用于接通所述第二输出晶体管的第四电压; 第一自举电路，放大第一电压的幅度并将其提供给第一输出晶体管; 以及基于第三输入脉冲信号的第一电压补偿电路，在所述第一输入脉冲信号的结束定时，使与所述第一电压中由于寄生物引起的电压波动相反的方向的电压变化 第一输入晶体管中的电容。

公开(公告)号：US08289239B2

公开(公告)日：2012-10-16

申请号：US12385692

申请日：2009-04-16

申请人： Takao Tanikame ,  Seiichiro Jinta

发明人： Takao Tanikame ,  Seiichiro Jinta

IPC分类号： G09G3/34

CPC分类号： G09G3/20 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0847 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/062 ,  G09G2330/02

摘要： Disclosed herein is a driving method for driving a display apparatus, the display apparatus including: N×M light emitting units; M scan lines; N data lines; a driving circuit provided for each of the light emitting units to serve as a circuit having a signal writing transistor, a device driving transistor, a capacitor and a first switch circuit; and a light emitting device.

摘要翻译： 这里公开了用于驱动显示装置的驱动方法，该显示装置包括：N×M个发光单元; M扫描线; N条数据线 为每个发光单元设置用作具有信号写入晶体管的电路的驱动电路，器件驱动晶体管，电容器和第一开关电路; 和发光装置。

公开(公告)号：US07830342B2

公开(公告)日：2010-11-09

申请号：US11882975

申请日：2007-08-08

申请人： Takahiko Mutsukura ,  Mitsuru Asano ,  Seiichiro Jinta ,  Masatsugu Tomida

发明人： Takahiko Mutsukura ,  Mitsuru Asano ,  Seiichiro Jinta ,  Masatsugu Tomida

IPC分类号： G09G3/30

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2320/043

摘要： A pixel circuit is disclosed. The pixel circuit includes, at least a drive transistor; an input transistor; a first switching transistor; a second switching transistor; a retention capacity; and an electro-optic device. The retention capacity is connected, at both ends, to a gate node and a source node, respectively, of the drive transistor. The electro-optic device has rectification properties, and is determined in intensity by a value of a drive current coming from the drive transistor whose source node is connected to an anode thereof. The input transistor is connected, at one current end, to the gate node of the drive transistor, and samples a video signal to the retention capacity during a predetermined sampling period. The first switching transistor is turned on before the sampling period, and connects the gate node of the drive transistor at a predetermined reference voltage.

摘要翻译： 公开了一种像素电路。 像素电路至少包括驱动晶体管; 输入晶体管; 第一开关晶体管; 第二开关晶体管; 保留能力; 和电光装置。 保持容量的两端分别连接到驱动晶体管的栅极节点和源极节点。 电光装置具有整流特性，并且通过源极节点连接到其阳极的驱动晶体管的驱动电流的值来确定强度。 输入晶体管在一个电流端连接到驱动晶体管的栅极节点，并在预定的采样周期内将视频信号采样到保持容量。 第一开关晶体管在采样周期之前导通，并将驱动晶体管的栅极节点连接到预定的参考电压。

公开(公告)号：US20100271111A1

公开(公告)日：2010-10-28

申请号：US12801819

申请日：2010-06-28

申请人： Seiichiro Jinta

发明人： Seiichiro Jinta

IPC分类号： G11C5/14 ,  H03K17/16

CPC分类号： H03K19/017

摘要： Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

摘要翻译： 本文公开了一种自举电路，其被配置为采用相同导电类型的第一，第二和第三晶体管，其中：将第一晶体管的栅极电极和第三晶体管的源极和漏极区域的特定的一个彼此连接的节点部分 当第三晶体管处于关断状态时，其处于浮置状态; 第二晶体管的栅电极连接到传送两个时钟信号中的另一个的时钟供应线; 并且在节点部分和第一电压供应线之间提供电压变化抑制电容器。

公开(公告)号：US07782121B2

公开(公告)日：2010-08-24

申请号：US12000702

申请日：2007-12-17

申请人： Seiichiro Jinta

发明人： Seiichiro Jinta

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  G09G3/20 ,  G09G2330/028 ,  H03K17/063

摘要： A voltage supply circuit including: first and second nodes; a predetermined potential; and an output transistor having its control terminal connected to the first node, its first terminal connected to the second node and its second terminal connected to an output terminal. The circuit further includes: a switching element which turns on in response to an active reset signal to connect the potential and the first and second nodes together; a first capacitor connected to the first node and supplied with a clock; a second capacitor connected to the second node and supplied with another clock; and an adjustment section adapted to adjust the clock amplitudes so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The reset signal is basically reverse in phase to the clocks.

摘要翻译： 一种电压供给电路，包括：第一和第二节点; 预定电位; 以及输出晶体管，其控制端子连接到第一节点，其第一端子连接到第二节点，其第二端子连接到输出端子。 电路还包括：开关元件，其响应于有效复位信号而接通，以将电位和第一和第二节点连接在一起; 连接到第一节点并提供时钟的第一电容器; 连接到第二节点并提供另一个时钟的第二电容器; 以及调整部分，其适于调整所述时钟幅度，使得所述第一和第二节点的电位以保持在其间的预定差异而变化。 复位信号基本上与时钟相反。

公开(公告)号：US20090201071A1

公开(公告)日：2009-08-13

申请号：US12320611

申请日：2009-01-30

申请人： Seiichiro Jinta

发明人： Seiichiro Jinta

IPC分类号： H03K19/017

CPC分类号： H03K19/017

摘要： Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

摘要翻译： 本文公开了一种自举电路，其被配置为采用相同导电类型的第一，第二和第三晶体管，其中：将第一晶体管的栅极电极和第三晶体管的源极和漏极区域的特定的一个彼此连接的节点部分 当第三晶体管处于关断状态时，其处于浮置状态; 第二晶体管的栅电极连接到传送两个时钟信号中的另一个的时钟供应线; 并且在节点部分和第一电压供应线之间提供电压变化抑制电容器。

公开(公告)号：US20080048955A1

公开(公告)日：2008-02-28

申请号：US11889357

申请日：2007-08-13

申请人： Akira Yumoto ,  Mitsuru Asano ,  Seiichiro Jinta

发明人： Akira Yumoto ,  Mitsuru Asano ,  Seiichiro Jinta

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G3/3291 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/06 ,  G09G2330/021

摘要： A pixel circuit is disposed where a scan line arranged in a row direction to supply a control signal and a data line arranged in a column direction to supply a video signal intersect each other. The pixel circuit includes: a sampling transistor; a drive transistor; a capacitor connected between the current path end of the sampling transistor and the gate of the drive transistor; and a light-emitting device connected to the current path end of the drive transistor. The pixel circuit connects the mobility with negative feedback during a mobility connection period.

摘要翻译： 像素电路设置在沿行方向布置的扫描线以提供控制信号和沿列方向布置以提供视频信号的数据线彼此相交的位置。 像素电路包括：采样晶体管; 驱动晶体管; 连接在采样晶体管的电流路径端与驱动晶体管的栅极之间的电容器; 以及连接到驱动晶体管的电流路径端的发光器件。 在移动连接期间，像素电路将移动性与负反馈连接。

公开(公告)号：US08427458B2

公开(公告)日：2013-04-23

申请号：US12457756

申请日：2009-06-19

申请人： Takao Tanikame ,  Seiichiro Jinta

发明人： Takao Tanikame ,  Seiichiro Jinta

IPC分类号： G06F3/038 ,  G09G3/30 ,  G11C19/00

CPC分类号： G09G3/3258 ,  G09G3/30 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2230/00 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0452 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0871 ,  G09G2310/0286

摘要： A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal STp+1 of a p+1'th shift register is situated between the start and end of a start pulse of the output signal STp of a p'th shift register, and one each of a first enable signal through a Q'th enable signal exist in sequence between the start of the start pulse of the output signal STp and the start of the start pulse of the output signal STp+1. The operations of a (p′, q)'th NAND circuit are restricted based on period identifying signals, such that the NAND circuit generates scanning signals based only on a portion of the output signal STP corresponding to the first start pulse, the signal obtained by inverting the output signal STp+1, and the q'th enable signal ENq.

摘要翻译： 扫描驱动电路包括移位寄存器单元和逻辑电路单元。 p + 1移位寄存器的输出信号STp + 1的起始脉冲的开始位于第p移位寄存器的输出信号STp的起始脉冲的开始和结束之间，并且每个 通过第Q个使能信号的第一使能信号依次存在于输出信号STp的起始脉冲的开始和输出信号STp + 1的起始脉冲的开始之间。 基于周期识别信号来限制（p'，q）'NAND电路的操作，使得NAND电路仅基于与第一起始脉冲对应的输出信号STP的一部分产生扫描信号，所获得的信号 通过反相输出信号STp + 1和第q个使能信号ENq。

公开(公告)号：US08400577B2

公开(公告)日：2013-03-19

申请号：US13418929

申请日：2012-03-13

申请人： Mitsuru Asano ,  Seiichiro Jinta ,  Masatsugu Tomida ,  Hiroshi Fujimura

发明人： Mitsuru Asano ,  Seiichiro Jinta ,  Masatsugu Tomida ,  Hiroshi Fujimura

IPC分类号： G02F1/136

CPC分类号： H01L27/3262 ,  G09G3/3233 ,  G09G3/3258 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  H01L27/1214 ,  H01L27/326 ,  H01L27/3265 ,  H01L27/3269 ,  H01L27/3276

摘要： Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

摘要翻译： 这里公开了一种显示装置，包括：具有像素电路矩阵的像素阵列，每个像素电路包括用于确定显示亮度水平的各个电光元件和用于驱动电光元件的相应驱动电路; 其中相邻的两个像素电路彼此配对，并且相邻的两个像素电路的每个驱动电路包括具有低浓度源极/漏极区域或偏移栅极结构的偏移区域的至少一个晶体管， 电光元件和相邻的两个像素电路的驱动电路被布置成使得互连至少一个晶体管的漏极区域和源极区域的线路平行于像素阵列的像素电路的像素列的方向延伸。

公开(公告)号：US08040163B2

公开(公告)日：2011-10-18

申请号：US12801819

申请日：2010-06-28

申请人： Seiichiro Jinta

发明人： Seiichiro Jinta

IPC分类号： H03K3/00

CPC分类号： H03K19/017

摘要： Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

摘要翻译： 本文公开了一种自举电路，其被配置为采用相同导电类型的第一，第二和第三晶体管，其中：将第一晶体管的栅极电极和第三晶体管的源极和漏极区域的特定的一个彼此连接的节点部分 当第三晶体管处于关断状态时，其处于浮置状态; 第二晶体管的栅电极连接到传送两个时钟信号中的另一个的时钟供应线; 并且在节点部分和第一电压供应线之间设置电压变化抑制电容器。