公开(公告)号：US20130153978A1

公开(公告)日：2013-06-20

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

公开(公告)号：US20130320424A1

公开(公告)日：2013-12-05

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，第二源极层基本上形成在第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US08878277B2

公开(公告)日：2014-11-04

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/76

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

摘要翻译： 3D非易失性存储器件包括管道浇口，至少一个第一沟道层，其包括形成在管道栅极中的第一管道沟道层，以及一对第一源极侧沟道层和与第一管道沟道连接的第一漏极侧沟道层 层，以及至少一个第二沟道层，其包括形成在管道浇口中并位于第一管道沟道层上的第二管道沟道层和连接到第二管道沟道层的一对第二源极侧沟道层和第二漏极侧沟道层 。

公开(公告)号：US08900948B2

公开(公告)日：2014-12-02

申请号：US13608341

申请日：2012-09-10

申请人： Seok-Min Jeon ,  Sun-Kok Hwang

发明人： Seok-Min Jeon ,  Sun-Kok Hwang

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833

摘要： A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.

摘要翻译： 一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个牺牲层，至少形成通过选择性蚀刻层间电介质层而使衬底暴露的通道孔 和牺牲层，在通过通道孔暴露的牺牲层的侧壁上形成保护层，在通道孔的侧壁上依次形成存储层和沟道层，形成穿透层间的狭缝孔 电介质层和通道孔两侧的牺牲层，去除通过狭缝孔露出的牺牲层，去除保护层，以及在除去牺牲层和保护层的空间中形成栅电极。

公开(公告)号：US08853767B2

公开(公告)日：2014-10-07

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，所述第二源极层基本上形成在所述第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130171787A1

公开(公告)日：2013-07-04

申请号：US13608341

申请日：2012-09-10

申请人： Seok-Min JEON ,  Sun-Kok Hwang

发明人： Seok-Min JEON ,  Sun-Kok Hwang

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833

摘要： A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.