公开(公告)号：US20110163789A1

公开(公告)日：2011-07-07

申请号：US12816581

申请日：2010-06-16

申请人： Tae-Sik Na ,  Seok-Hun Hyun

发明人： Tae-Sik Na ,  Seok-Hun Hyun

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00058

摘要： Provided are a duty cycle correction circuit and method for correcting a duty cycle, and a semiconductor device including the duty cycle correction circuit. The duty cycle correction circuit includes a code generator configured to generate a first and a second duty code for adjusting the duty cycle of a clock to a target duty cycle, and a duty cycle corrector including a plurality of inverter circuits connected in series and whose driving capabilities are adjusted in response to the first and second duty code, wherein the duty cycle corrector is configured to correct the duty cycle of the clock based on the driving capabilities of the inverter circuits and to output a corrected clock.

摘要翻译： 提供了一种用于校正占空比的占空比校正电路和方法，以及包括占空比校正电路的半导体器件。 占空比校正电路包括代码发生器，其被配置为产生用于将时钟的占空比调整为目标占空比的第一和第二占空比，以及占空比校正器，其包括串联连接并且驱动的多个反相器电路 响应于第一和第二占空比调整功能，其中占空比校正器被配置为基于反相器电路的驱动能力校正时钟的占空比并输出校正的时钟。

公开(公告)号：US20100156488A1

公开(公告)日：2010-06-24

申请号：US12644044

申请日：2009-12-22

申请人： Yang-ki Kim ,  Seok-hun Hyun

发明人： Yang-ki Kim ,  Seok-hun Hyun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03K2005/00202 ,  H03K2005/00208

摘要： The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

摘要翻译： DLL电路包括根据外部输入的列地址选通写入延迟（CWL）信号来控制单位延迟电路的偏置电流的控制电路，和/或DCC控制电路，其调节DCC的DCC电流的步长，根据 外部输入列地址选通写入延迟（CWL）信号。 CWL信号可以由半导体存储器件输入，并且可以指示列地址选通写入半导体存储器件的延迟。 半导体存储器件可以是双倍数据速率（DDR）同步DRAM（SDRAM）器件。

公开(公告)号：US09466393B2

公开(公告)日：2016-10-11

申请号：US14997041

申请日：2016-01-15

申请人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C17/18 ,  G11C29/04 ,  G11C29/44 ,  G11C29/00 ,  G11C17/16 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

摘要翻译： 能够拯救包装后发生的缺陷特性的存储器件包括包括多个存储单元的存储单元阵列和包括至少一个反熔丝的反熔断电路单元。 反熔丝电路单元将存储单元阵列的缺陷单元地址存储在至少一个反熔丝中，并将缺陷单元地址读取到外部源。 反熔丝电路单元将不良特性代码存储在至少一个反熔丝中，其中不良特性代码与定时参数规格，刷新规格，输入/输出（I / O）触发电压 规格和数据训练规范。 并将缺陷特征码输出到外部源。

公开(公告)号：US20130198587A1

公开(公告)日：2013-08-01

申请号：US13611566

申请日：2012-09-12

申请人： JEONG-KYOUM KIM ,  JUNG HWAN CHOI ,  SEOK HUN HYUN ,  SEONG JIN JANG

发明人： JEONG-KYOUM KIM ,  JUNG HWAN CHOI ,  SEOK HUN HYUN ,  SEONG JIN JANG

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  H03M13/356 ,  H03M13/3707

摘要： A memory system includes a semiconductor memory device, a memory controller for controlling the semiconductor memory device, and a memory buffer connected between the semiconductor memory device and the memory controller. The memory buffer is configured to perform error correction coding (ECC) on first data that is received from the memory controller to be stored in the semiconductor memory device and to perform ECC on second data read from the semiconductor memory device.

摘要翻译： 存储器系统包括半导体存储器件，用于控制半导体存储器件的存储器控​​制器以及连接在半导体存储器件和存储器控制器之间的存储器缓冲器。 存储器缓冲器被配置为对从存储器控制器接收的第一数据执行存储在半导体存储器件中的纠错编码（ECC），并对从半导体存储器件读取的第二数据执行ECC。

公开(公告)号：US09269457B2

公开(公告)日：2016-02-23

申请号：US13777428

申请日：2013-02-26

申请人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

公开(公告)号：US20100097111A1

公开(公告)日：2010-04-22

申请号：US12588571

申请日：2009-10-20

申请人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

发明人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

摘要翻译： 一种延迟锁定环路，适于延迟外部时钟信号并输出​​内部时钟信号，所述延迟锁定环路包括更新信号发生器，所述更新信号发生器输出被选择性地激活和去激活的更新信号，所述更新信号在所述更新信号 被激活，并且当更新信号被去激活时不活动，复制路径延迟内部时钟信号延迟半导体器件的正常路径的延迟时间，以在更新信号被激活时输出复制内部时钟信号;控制信号发生器 适于改变并根据外部和复制内部时钟信号之间的相位差输出延迟控制信号，以及可变延迟电路，其适于将外部时钟信号延迟与延迟控制信号相对应的时间，并输出 内部时钟信号。

公开(公告)号：US20160133335A1

公开(公告)日：2016-05-12

申请号：US14997041

申请日：2016-01-15

申请人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C17/18 ,  G11C17/16 ,  G11C29/00

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

摘要翻译： 能够拯救包装后发生的缺陷特性的存储器件包括包括多个存储单元的存储单元阵列和包括至少一个反熔丝的反熔断电路单元。 反熔丝电路单元将存储单元阵列的缺陷单元地址存储在至少一个反熔丝中，并将缺陷单元地址读取到外部源。 反熔丝电路单元将不良特性代码存储在至少一个反熔丝中，其中不良特性代码与定时参数规格，刷新规格，输入/输出（I / O）触发电压 规格和数据训练规范。 并将缺陷特征码输出到外部源。

公开(公告)号：US20130223171A1

公开(公告)日：2013-08-29

申请号：US13777428

申请日：2013-02-26

申请人： Jeong-Kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-Kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C29/04

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

摘要翻译： 能够拯救包装后发生的缺陷特性的存储器件包括包括多个存储单元的存储单元阵列和包括至少一个反熔丝的反熔断电路单元。 反熔丝电路单元将存储单元阵列的缺陷单元地址存储在至少一个反熔丝中，并将缺陷单元地址读取到外部源。 反熔丝电路单元将不良特性代码存储在至少一个反熔丝中，其中不良特性代码与定时参数规格，刷新规格，输入/输出（I / O）触发电压 规格和数据训练规范。 并将缺陷特征码输出到外部源。

公开(公告)号：US08049545B2

公开(公告)日：2011-11-01

申请号：US12644044

申请日：2009-12-22

申请人： Yang-ki Kim ,  Seok-hun Hyun

发明人： Yang-ki Kim ,  Seok-hun Hyun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03K2005/00202 ,  H03K2005/00208

摘要： The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

摘要翻译： DLL电路包括根据外部输入的列地址选通写入延迟（CWL）信号来控制单位延迟电路的偏置电流的控制电路，和/或DCC控制电路，其调节DCC的DCC电流的步长，根据 外部输入列地址选通写入延迟（CWL）信号。 CWL信号可以由半导体存储器件输入，并且可以指示列地址选通写入半导体存储器件的延迟。 半导体存储器件可以是双倍数据速率（DDR）同步DRAM（SDRAM）器件。

公开(公告)号：US07961018B2

公开(公告)日：2011-06-14

申请号：US12588571

申请日：2009-10-20

申请人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

发明人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

摘要翻译： 一种延迟锁定环路，适于延迟外部时钟信号并输出​​内部时钟信号，所述延迟锁定环路包括更新信号发生器，所述更新信号发生器输出被选择性地激活和去激活的更新信号，所述更新信号在所述更新信号 被激活，并且当更新信号被去激活时不活动，复制路径延迟内部时钟信号延迟半导体器件的正常路径的延迟时间，以在更新信号被激活时输出复制内部时钟信号;控制信号发生器 适于改变并根据外部和复制内部时钟信号之间的相位差输出延迟控制信号，以及可变延迟电路，其适于将外部时钟信号延迟与延迟控制信号相对应的时间，并输出 内部时钟信号。