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    Pulse radar receiver
    2.
    发明授权
    Pulse radar receiver 有权
    脉冲雷达接收机

    公开(公告)号：US08754806B2

    公开(公告)日：2014-06-17

    申请号：US13316381

    申请日：2011-12-09

    申请人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

    发明人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

    IPC分类号： G01S7/285 ,  G01S7/00 ,  G01S13/10

    CPC分类号： G01S7/292

    摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.

    摘要翻译： 脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及 产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。 因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。 因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。 因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。

    Fractional digital PLL with analog phase error compensator
    4.
    发明授权
    Fractional digital PLL with analog phase error compensator 有权
    具有模拟相位误差补偿器的分数字数字PLL

    公开(公告)号：US08432199B2

    公开(公告)日：2013-04-30

    申请号：US13310581

    申请日：2011-12-02

    申请人： Ja Yol Lee ,  Seong-Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seong-Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0802 ,  H03L7/085 ,  H03L2207/50

    摘要： Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

    摘要翻译： 公开了具有模拟相位误差补偿器的分数字数字锁相环。 具有模拟相位误差补偿器的数字锁相环可以通过模拟相位误差补偿器进行分数相位误差检测和补偿，从而降低功耗，功耗噪声和瞬态电流噪声，同时提高相位误差检测分辨率。

    Time-to-digital converter and all digital phase-locked loop including the same
    5.
    发明授权
    Time-to-digital converter and all digital phase-locked loop including the same 有权
    时间到数字转换器和所有数字锁相环包括相同的

    公开(公告)号：US08344772B2

    公开(公告)日：2013-01-01

    申请号：US12956498

    申请日：2010-11-30

    申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

    摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

    摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

    Frequency synthesizer including a digital lock detector
    6.
    发明授权
    Frequency synthesizer including a digital lock detector 有权
    频率合成器包括数字锁定检测器

    公开(公告)号：US08013641B1

    公开(公告)日：2011-09-06

    申请号：US13098332

    申请日：2011-04-29

    申请人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Ja Yol Lee ,  Seong Do Kim ,  Mun Yang Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03B21/00

    CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

    摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

    摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

    DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME
    7.
    发明申请
    DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
    使用数字锁定检测器和频率合成器

    公开(公告)号：US20110204944A1

    公开(公告)日：2011-08-25

    申请号：US13098332

    申请日：2011-04-29

    申请人： Ja Yol LEE ,  Seong Do KIM ,  Mun Yang PARK ,  Cheon Soo KIM ,  Hyun Kyu YU

    发明人： Ja Yol LEE ,  Seong Do KIM ,  Mun Yang PARK ,  Cheon Soo KIM ,  Hyun Kyu YU

    IPC分类号： H03L7/08

    CPC分类号： H03L7/16 ,  H03L7/095 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/50

    摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

    摘要翻译： 提供了数字锁定检测器和使用该锁定检测器的频率合成器。 数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

    Frame synchronizing device
    9.
    发明授权
    Frame synchronizing device 失效
    帧同步装置

    公开(公告)号：US5710774A

    公开(公告)日：1998-01-20

    申请号：US555852

    申请日：1995-11-13

    申请人： Chung-Wook Suh ,  Seong-Do Kim

    发明人： Chung-Wook Suh ,  Seong-Do Kim

    IPC分类号： H04M7/08 ,  H04J3/00 ,  H04J3/06 ,  H04L7/08

    CPC分类号： H04J3/0608

    摘要： A frame synchronizing device for discriminating a time slot location for each channel of time-division multiplexed signals is disclosed. The frame synchronizing device according to the invention processes time-division multiplexed signals in parallel in a STM-4C(Synchronous Transport Module-4 Concatenation) of the Broadband Integrated Service Digital Network according to the ITU-T recommendation, such that the searching of frame synchronization can be achieved by detecting frame bytes on data being received at a high speed in the STM-4C structure to align the bytes based on the detected time interval, converting the frame data into the 8-bits parallel data and then detecting, in sequence, the frame bytes at a lower speed clock being divided by 8, thereby providing a simplified, less power consumptive frame synchronizing device in the STM-4C structure according to the ITU-T recommendation.

    摘要翻译： 公开了一种用于区分时分复用信号的每个信道的时隙位置的帧同步装置。 根据本发明的帧同步装置根据ITU-T建议在宽带综合业务数字网络的STM-4C（同步传输模块-4级联）中并行处理时分复用信号，使得搜索帧 可以通过检测在STM-4C结构中高速接收的数据上的帧字节来实现同步，以便根据检测到的时间间隔对齐字节，将帧数据转换成8位并行数据，然后依次检测 ，将低速时钟的帧字节除以8，从而根据ITU-T推荐，在STM-4C结构中提供简化的，较少功耗的帧同步装置。

    Apparatus for automatic gain control and wireless receiver employing the same
    10.
    发明授权
    Apparatus for automatic gain control and wireless receiver employing the same 失效
    用于自动增益控制的装置和采用该装置的无线接收器

    公开(公告)号：US07933369B2

    公开(公告)日：2011-04-26

    申请号：US11635197

    申请日：2006-12-07

    申请人： Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    发明人： Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

    IPC分类号： H04L27/08

    CPC分类号： H04L27/0002 ,  H03G3/001 ,  H03G3/3068

    摘要： Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.

    摘要翻译： 提供了广泛用于无线通信系统的接收机中的自动增益控制（AGC）的装置。 无线通信系统的接收机包括：设置在无线信号的路径中的步进可变增益放大器和模拟可变增益放大器，并放大无线信号; 模拟增益控制单元，用于产生用于反馈控制模拟可变增益放大器的放大值的增益控制电压; 数字增益控制单元，用于接收控制电压并产生确定阶跃可变增益放大器的放大值的数字代码。 如上所述构成的AGC装置可以通过有效地运行模拟域中的AGC环路来降低功耗和装置数量，并且可以在适当地控制步进增益放大器和模拟增益放大器的结构中以低成本实现。