公开(公告)号：US6109201A

公开(公告)日：2000-08-29

申请号：US10395

申请日：1998-01-21

申请人： Dusan Petranovic ,  Ranko Scepanovic ,  Stanislav V. Aleshin ,  Mikhail Grinchuk ,  Sergei Gashov

发明人： Dusan Petranovic ,  Ranko Scepanovic ,  Stanislav V. Aleshin ,  Mikhail Grinchuk ,  Sergei Gashov

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided. The critical path is defined by the fact that the delay at each block is accumulated because each block has to wait for the output signal of the preceding block to use as its input signal. After the resynthesis of the blocks, none of the blocks need to wait for the output signal of its preceding block because each of the resynthesized blocks has the output for all possible inputs values (0 and 1). Thus, the signal delay at each block is not accumulated; rather, the only accumulated delay is the delay of the multiplexors used to select the correct output. The result is a dramatically reduced critical path delay.

摘要翻译： 集成电路芯片（IC）需要适当放置多个单元（电路组件组）和复杂的导线布线来连接单元。 IC的设计需要满足实际的限制，其中之一是IC的性能，或集成电路从输入信号可用时产生输出信号所需的时间段。 通常，集成电路的性能由称为关键路径的信号的最慢路径决定。 关键路径通常只是IC的一小部分。 本发明公开了一种用于变换包括关键路径的电路的方法和装置，从而提高了整个IC的性能。 通过分割或阻塞构成关键路径的单元来执行转换。 然后，用提供数字0和数字1值的再合成电路对每个块进行变换或替换。 关键路径由每个块的延迟积累的事实定义，因为每个块必须等待前一块的输出信号用作其输入信号。 在块的再合成之后，没有一个块需要等待其前一块的输出信号，因为每个再合并块具有用于所有可能的输入值（0和1）的输出。 因此，每个块的信号延迟不被累加; 相反，唯一累积的延迟是用于选择正确输出的多路复用器的延迟。 结果是大大减少了关键路径延迟。