公开(公告)号：US20090037859A1

公开(公告)日：2009-02-05

申请号：US11831745

申请日：2007-07-31

申请人： Shashidar Anil Thakur ,  Rahul Hari Dani ,  Ramnath N. Rao

发明人： Shashidar Anil Thakur ,  Rahul Hari Dani ,  Ramnath N. Rao

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constraints, on random values for signals to be input to the circuit during simulation of the design. Application of the rules identifies one or more templates of goal(s) to be met. The computer is programmed to automatically use constraint(s) and template(s) to instantiate goal(s) in memory. Each goal identifies a signal to be input to the circuit, and defines a counter for a value of the signal. The goals are used in the normal manner, i.e. used to measure coverage of functional verification during simulation of the design of the circuit.

摘要翻译： 计算机被编程为在存储器中自动生成，通过使用以正常方式指定的约束来对电路设计进行功能验证的目标。 具体而言，在设计仿真期间，将规定的规则集合自动应用于要输入到电路的信号的随机值的约束。 规则的应用确定要满足的目标的一个或多个模板。 计算机被编程为自动使用约束和模板来实例化存储器中的目标。 每个目标识别要输入到电路的信号，并且定义用于信号值的计数器。 目标以正常方式使用，即用于在模拟电路设计期间测量功能验证的覆盖范围。