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1.发明申请Non-invasiv, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入式，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US20090179660A1
公开(公告)日：2009-07-16
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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2.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07808263B2
公开(公告)日：2010-10-05
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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3.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07521951B1
公开(公告)日：2009-04-21
申请号：US11402508
申请日：2006-04-12
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种测试集成电路的内部块的方法包括在与其他操作模式中的条件相比较下，在测试模式中在更严格的条件下启动测试模式并验证集成电路的操作，使得集成电路 在另一个操作模式下保证。 在指示内部块的操作的测试模式中，选择性地从所选择的引脚输出测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一个信号。
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