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    METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE
    5.
    发明申请
    METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE 有权
    使用可分散间隔技术形成高分辨率半导体器件的方法

    公开(公告)号：US20130095620A1

    公开(公告)日：2013-04-18

    申请号：US13275766

    申请日：2011-10-18

    Applicant: Jan Hoentschel ,  Stefan Flachowsky ,  Shiang Yang Ong

    Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Shiang Yang Ong

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

    Abstract: In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer.

    Abstract translation: 在一个示例中，本文公开的方法包括以下步骤：在衬底上方形成第一衬垫层，并在PMOS晶体管和NMOS晶体管之上形成栅极结构之上，并且在形成扩展注入区域和晕圈注入区域之后，形成第一衬垫 靠近PMOS和NMOS晶体管的栅极结构，在用于PMOS和NMOS晶体管的衬底中形成深源极/漏极注入区域，去除第一间隔物，并且在移除第一间隔物之后，在相邻栅极之间形成材料层 结构，其中所述材料层至少占据由所述第一间隔件先前占据的空间。

    Selective STI stress relaxation through ion implantation
    6.
    发明授权
    Selective STI stress relaxation through ion implantation 有权
    通过离子注入选择性STI应力松弛

    公开(公告)号：US07727856B2

    公开(公告)日：2010-06-01

    申请号：US11615980

    申请日：2006-12-24

    Applicant: Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    Inventor： Lee Wee Teo ,  Shiang Yang Ong ,  Jae Gon Lee ,  Vincent Leong ,  Elgin Quek ,  Dong Kyun Sohn

    IPC: H01L21/76

    CPC classification number: H01L27/092 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7846

    Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

    Abstract translation: 第一示例性实施例包括以下步骤和由其形成的结构。 在衬底内形成具有相对侧壁的沟槽。 在相对的沟槽侧壁上形成具有固有应力的应力层。 应力层在沟槽侧壁上具有应力层侧壁。 将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力 的应力层部分被松弛。

    End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping
    8.
    发明授权
    End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping 有权
    使用化学气相沉积（CVD）替代碳掺杂的范围终点（EOR）二次缺陷工程

    公开(公告)号：US07400018B2

    公开(公告)日：2008-07-15

    申请号：US11462846

    申请日：2006-08-07

    Applicant: Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

    Inventor： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

    IPC: H01L29/76 ,  H01L29/94

    CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/6659

    Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

    Abstract translation: 实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。 提供体硅衬底。 在体硅衬底上沉积碳掺杂硅层。 生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。 通过以下步骤在起始晶片上制造集成电路器件。 在起始晶片上形成栅电极。 将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。 植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作 用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

    End of range (EOR) secondary defect engineering using substitutional carbon doping
    9.
    发明授权
    End of range (EOR) secondary defect engineering using substitutional carbon doping 有权
    使用替代碳掺杂的范围终点（EOR）二次缺陷工程

    公开(公告)号：US07109099B2

    公开(公告)日：2006-09-19

    申请号：US10688047

    申请日：2003-10-17

    Applicant: Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

    Inventor： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

    IPC: H01L21/425 ,  H01L21/36 ,  H01L21/20 ,  H01L21/265

    CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/6659

    Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

    Abstract translation: 实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。 提供体硅衬底。 在体硅衬底上沉积碳掺杂硅层。 生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。 通过以下步骤在起始晶片上制造集成电路器件。 在起始晶片上形成栅电极。 将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。 植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作 用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

    Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
    10.
    发明授权
    Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process 有权
    通过进行氟注入工艺来调整具有高k /金属层栅极结构的半导体器件功函数的方法

    公开(公告)号：US08828834B2

    公开(公告)日：2014-09-09

    申请号：US13494686

    申请日：2012-06-12

    Applicant: Shesh Mani Pandey ,  Shiang Yang Ong ,  Jan Hoentschel

    Inventor： Shesh Mani Pandey ,  Shiang Yang Ong ,  Jan Hoentschel

    IPC: H01L21/336

    CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

    Abstract: One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed.

    Abstract translation: 本文公开的一种说明性方法包括在半导体衬底上形成多层材料，其中多层材料将包括用于晶体管的栅极结构，执行氟离子注入工艺以将氟离子注入到至少一个 多个材料层，执行至少一个离子注入工艺以将P型掺杂剂材料或N型掺杂剂材料中的一种注入到衬底中以形成用于晶体管的源极/漏极区域，并且在所述晶体管的后面执行退火处理 氟离子注入工艺和至少一个离子注入工艺。

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