公开(公告)号：US20100194421A1

公开(公告)日：2010-08-05

申请号：US12365900

申请日：2009-02-05

申请人： SATOSHI IWAMOTO ,  SHIGEKI TAKIZAWA ,  KOICHI YATSUKA ,  TOSHIO MATSUURA

发明人： SATOSHI IWAMOTO ,  SHIGEKI TAKIZAWA ,  KOICHI YATSUKA ,  TOSHIO MATSUURA

IPC分类号： G01R31/02 ,  G06F1/12

CPC分类号： G01R31/31919 ,  G01R31/31922

摘要： Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section.

摘要翻译： 提供了一种测试被测设备的测试装置，包括产生用于测试被测设备的测试图案的模式产生部分; 信号提供部分，向所述被测器件供给与测试图案对应的测试信号; 触发生成部，其将触发信号提供给与被测设备连接的外部仪器; 以及同步控制部，其基于由所述图案生成部生成的所述测试图案的至少一部分，向所述触发生成部输出指示所述触发信号的生成的同步信号。

公开(公告)号：US06275057B1

公开(公告)日：2001-08-14

申请号：US09115661

申请日：1998-07-15

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G01R2302

CPC分类号： G01R31/31709 ,  G01R31/31922

摘要： A semiconductor test system having a high repetition rate and small jitter clock generator for supplying the clock signal to a device under test (DUT). The semiconductor test system includes a clock generator for generating a reference clock signal, a frame processor for producing a clock signal of predetermined waveform based on the reference clock signal from the clock generator, a phase lock loop (PLL) circuit for generating a clock signal based on the clock signal from the frame processor where the frequency generated by the PLL circuit is higher than that of the clock signal from the frame processor, and a driver for directly receiving the clock signal from the PLL circuit to apply the clock signal to the DUT with a predetermined amplitude.

摘要翻译： 具有高重复率的半导体测试系统和用于将时钟信号提供给被测器件（DUT）的小抖动时钟发生器。 半导体测试系统包括用于产生参考时钟信号的时钟发生器，用于基于来自时钟发生器的参考时钟信号产生预定波形的时钟信号的帧处理器，用于产生时钟信号的锁相环（PLL）电路 基于来自帧处理器的时钟信号，其中由PLL电路产生的频率高于来自帧处理器的时钟信号的时钟信号;以及驱动器，用于直接从PLL电路接收时钟信号以将时钟信号施加到 DUT具有预定的幅度。

公开(公告)号：US07802160B2

公开(公告)日：2010-09-21

申请号：US11951335

申请日：2007-12-06

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G01R31/28

CPC分类号： G01R31/3191 ,  G01R31/31922

摘要： A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

摘要翻译： 提供了一种测试被测设备的测试设备，包括：将测试信号提供给被测设备的相应引脚的驱动器部分，根据被测设备的通过/失败进行判断的判断部分; 响应于测试信号由被测器件输出的响应信号，检测由驱动器部分输出的信号的直流电压的电压测量部分以及调节由所述驱动器部分输出的信号的占空比的输出侧调整部分 驱动器部分根据由电压测量部分检测到的直流电压。

公开(公告)号：US07350123B2

公开(公告)日：2008-03-25

申请号：US10913763

申请日：2004-08-06

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G01R31/28

CPC分类号： G01R31/3191

摘要： A test apparatus includes a test module including a correcting unit for correcting the timing at which the test signal is to be supplied to the device under test or a voltage level of the test signal to the device under test, a correction value holding unit for holding a correction value used for a correction by the correcting unit, and an identification information storing unit for storing test module identification information, which is identification information of the test module, a correction value database for storing the correction value to be held by the correction value holding unit of the test module identified by the test module identification information, in order that the correction value corresponds to the test module identification information, and control means for retrieving the correction value stored by the correction value database, wherein the correction value corresponds to the test module identification information stored by the identification information storing unit, and controlling the correction value holding unit to hold the correction value.

摘要翻译： 一种测试装置，包括测试模块，该测试模块包括校正单元，用于校正将测试信号提供给被测设备的定时或测试信号的电压电平与被测设备的校正值， 用于校正单元的校正的校正值，以及用于存储作为测试模块的识别信息的测试模块识别信息的识别信息存储单元，用于存储要由校正值保持的校正值的校正值数据库 由测试模块识别信息识别的测试模块的保持单元，以便校正值对应于测试模块识别信息，以及用于检索由校正值数据库存储的校正值的控制装置，其中校正值对应于 测试模块识别信息由存储的识别信息存储 并且控制校正值保持单元以保持校正值。

公开(公告)号：US20050034043A1

公开(公告)日：2005-02-10

申请号：US10913763

申请日：2004-08-06

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G01R31/319 ,  G01R31/28 ,  G06F11/00 ,  G06F11/10

CPC分类号： G01R31/3191

摘要： A test apparatus includes a test module including a correcting unit for correcting the timing at which the test signal is to be supplied to the device under test or a voltage level of the test signal to the device under test, a correction value holding unit for holding a correction value used for a correction by the correcting unit, and an identification information storing unit for storing test module identification information, which is identification information of the test module, a correction value database for storing the correction value to be held by the correction value holding unit of the test module identified by the test module identification information, in order that the correction value corresponds to the test module identification information, and control means for retrieving the correction value stored by the correction value database, wherein the correction value corresponds to the test module identification information stored by the identification information storing unit, and controlling the correction value holding unit to hold the correction value.

摘要翻译： 一种测试装置，包括测试模块，该测试模块包括校正单元，用于校正将测试信号提供给被测设备的定时或测试信号的电压电平与被测设备的校正值， 用于校正单元的校正的校正值，以及用于存储作为测试模块的识别信息的测试模块识别信息的识别信息存储单元，用于存储要由校正值保持的校正值的校正值数据库 由测试模块识别信息识别的测试模块的保持单元，以便校正值对应于测试模块识别信息，以及用于检索由校正值数据库存储的校正值的控制装置，其中校正值对应于 测试模块识别信息由存储的识别信息存储 并且控制校正值保持单元以保持校正值。

公开(公告)号：US07876118B2

公开(公告)日：2011-01-25

申请号：US12365900

申请日：2009-02-05

申请人： Satoshi Iwamoto ,  Shigeki Takizawa ,  Koichi Yatsuka ,  Toshio Matsuura

发明人： Satoshi Iwamoto ,  Shigeki Takizawa ,  Koichi Yatsuka ,  Toshio Matsuura

IPC分类号： G01R31/26

CPC分类号： G01R31/31919 ,  G01R31/31922

摘要： Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section.

摘要翻译： 提供了一种测试被测设备的测试装置，包括产生用于测试被测设备的测试图案的模式产生部分; 信号提供部分，向所述被测器件供给与所述测试图案相对应的测试信号; 触发生成部，其将触发信号提供给与被测设备连接的外部仪器; 以及同步控制部，其基于由所述图案生成部生成的所述测试图案的至少一部分，向所述触发生成部输出指示所述触发信号的生成的同步信号。

公开(公告)号：US07768255B2

公开(公告)日：2010-08-03

申请号：US12199811

申请日：2008-08-28

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G01R31/26

CPC分类号： G01R31/31725

摘要： There is provided an interconnection substrate used in skew adjustment between output pins in a test apparatus, the test apparatus supplying a test signal to a device under test to test the device under test, the interconnection substrate including: a first terminal coupled to a first output pin that outputs the test signal; a second terminal coupled to a second output pin that outputs the test signal; a first interconnection connecting the first terminal to a bonding node; a second interconnection connecting the second terminal to the bonding node; and a third interconnection connecting the bonding node to an output node, where the first interconnection and the second interconnection have a length equal to each other.

摘要翻译： 提供了一种用于在测试装置中的输出引脚之间进行偏斜调整的互连基板，所述测试装置向被测器件提供测试信号以测试被测器件，所述互连衬底包括：耦合到第一输出端的第一端子 引脚输出测试信号; 耦合到输出测试信号的第二输出引脚的第二端子; 将所述第一端子连接到接合节点的第一互连件; 将所述第二终端连接到所述绑定节点的第二互连; 以及将所述接合节点连接到输出节点的第三互连，其中所述第一互连和第二互连具有彼此相等的长度。

公开(公告)号：US20100052723A1

公开(公告)日：2010-03-04

申请号：US12199811

申请日：2008-08-28

申请人： SHIGEKI TAKIZAWA

发明人： SHIGEKI TAKIZAWA

IPC分类号： G01R31/26

CPC分类号： G01R31/31725

摘要： There is provided an interconnection substrate used in skew adjustment between output pins in a test apparatus, the test apparatus supplying a test signal to a device under test to test the device under test, the interconnection substrate including: a first terminal coupled to a first output pin that outputs the test signal; a second terminal coupled to a second output pin that outputs the test signal; a first interconnection connecting the first terminal to a bonding node; a second interconnection connecting the second terminal to the bonding node; and a third interconnection connecting the bonding node to an output node, where the first interconnection and the second interconnection have a length equal to each other.

摘要翻译： 提供了一种用于在测试装置中的输出引脚之间进行偏斜调整的互连衬底，所述测试装置向被测器件提供测试信号以测试被测器件，所述互连衬底包括：耦合到第一输出端的第一端子 引脚输出测试信号; 耦合到输出测试信号的第二输出引脚的第二端子; 将所述第一端子连接到接合节点的第一互连件; 将所述第二终端连接到所述绑定节点的第二互连; 以及将所述接合节点连接到输出节点的第三互连，其中所述第一互连和第二互连具有彼此相等的长度。

公开(公告)号：US20090150733A1

公开(公告)日：2009-06-11

申请号：US11951335

申请日：2007-12-06

申请人： Shigeki Takizawa

发明人： Shigeki Takizawa

IPC分类号： G06F11/00

CPC分类号： G01R31/3191 ,  G01R31/31922

摘要： A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

摘要翻译： 提供了一种测试被测设备的测试设备，包括：将测试信号提供给被测设备的相应引脚的驱动器部分，根据被测设备的通过/失败进行判断的判断部分; 响应于测试信号由被测器件输出的响应信号，检测由驱动器部分输出的信号的直流电压的电压测量部分以及调节由所述驱动器部分输出的信号的占空比的输出侧调整部分 驱动器部分根据由电压测量部分检测到的直流电压。