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    Flash memory apparatus with programming voltage control generators
    1.
    发明授权
    Flash memory apparatus with programming voltage control generators 有权
    带编程电压控制发生器的闪存设备

    公开(公告)号：US08705289B2

    公开(公告)日：2014-04-22

    申请号：US13344621

    申请日：2012-01-06

    申请人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

    发明人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C16/12

    摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

    摘要翻译： 提供一种闪存装置。 闪存装置包括多个存储单元和多个编程电压控制发生器。 每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。 每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。 预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。 在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

    Logic-based multiple time programming memory cell
    2.
    发明授权
    Logic-based multiple time programming memory cell 有权
    基于逻辑的多时间编程存储单元

    公开(公告)号：US08625350B2

    公开(公告)日：2014-01-07

    申请号：US13485920

    申请日：2012-06-01

    申请人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

    发明人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

    摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

    摘要翻译： 非易失性存储器系统包括一个或多个非易失性存储器单元。 每个非易失性存储单元提供浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。 耦合装置位于第一导电区域中。 第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。 第二浮栅晶体管位于第三导电区域中。 这种非易失性存储单元进一步提供两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。 浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

    Non-volatile semiconductor memory device with intrinsic charge trapping layer
    3.
    发明授权
    Non-volatile semiconductor memory device with intrinsic charge trapping layer 有权
    具有固有电荷俘获层的非易失性半导体存储器件

    公开(公告)号：US08390056B2

    公开(公告)日：2013-03-05

    申请号：US13253083

    申请日：2011-10-05

    申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

    发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

    IPC分类号： H01L29/788

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

    摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

    摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

    NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY
    4.
    发明申请
    NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY 有权
    非易失性存储器单元具有改进的传感和可靠性

    公开(公告)号：US20120273860A1

    公开(公告)日：2012-11-01

    申请号：US13541755

    申请日：2012-07-04

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

    IPC分类号： H01L27/06

    CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

    摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

    摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

    Single polysilicon layer non-volatile memory and operating method thereof
    5.
    发明授权
    Single polysilicon layer non-volatile memory and operating method thereof 有权
    单晶硅层非易失性存储器及其操作方法

    公开(公告)号：US08199578B2

    公开(公告)日：2012-06-12

    申请号：US12792746

    申请日：2010-06-03

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： H01L27/11558 ,  G11C16/0433 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    摘要： A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

    摘要翻译： 提供具有浮置栅晶体管，编程门和控制栅极的单多晶硅层非易失性存储器。 浮栅晶体管具有浮置栅极和隧穿介电层。 浮栅设置在基板上。 隧道介电层设置在浮置栅极和衬底之间。 编程栅极，控制栅极和擦除栅极分别设置在由隧道电介质层分离的浮置栅极下的衬底中。 因此，在编程操作和擦除操作期间，通过隧道介电层的不同区域注入和排出电荷，以增加非易失性存储器的可靠性。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER
    6.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER 有权
    具有内置电荷捕获层的非易失性半导体存储器件

    公开(公告)号：US20110024823A1

    公开(公告)日：2011-02-03

    申请号：US12633780

    申请日：2009-12-08

    申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

    发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

    摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

    摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

    Single poly non-volatile memory
    10.
    发明授权
    Single poly non-volatile memory 有权
    单个多重非易失性存储器

    公开(公告)号：US07209392B2

    公开(公告)日：2007-04-24

    申请号：US10905736

    申请日：2005-01-19

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Hong-Ping Tsai

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Hong-Ping Tsai

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0441 ,  H01L27/115

    摘要： An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

    摘要翻译： 可擦除可编程非易失性存储单元包含离子阱; 包括选择栅极的第一选择晶体管，形成在所述离子阱中的源极/漏极以及在其源极和漏极之间形成的沟道区域; 具有漏极的第一浮栅晶体管，耦合到所述第一选择晶体管的漏极的源极，形成在其漏源和源极之间的第一浮置栅极沟道区和覆盖所述浮置栅极沟道区的公共浮动栅; 包括选择栅极的第二选择晶体管，形成在离子阱中的源极/漏极，以及在其源极和漏极之间形成的沟道区域; 以及第二浮栅晶体管，其具有漏极，耦合到所述第二选择晶体管的漏极的源极，形成在其漏极和源极之间的第二浮置栅极沟道区域以及覆盖所述第二浮置栅极沟道区域的所述公共浮动栅极。