-
公开(公告)号：US20130119371A1
公开(公告)日：2013-05-16
申请号：US13444860
申请日：2012-04-12
申请人： Hao-Lin Chiu , Chi-Jui Lin , Shu-Wei Tsao , Chun-Nan Lin , Po-Liang Yeh , Shine-Kai Tseng
发明人： Hao-Lin Chiu , Chi-Jui Lin , Shu-Wei Tsao , Chun-Nan Lin , Po-Liang Yeh , Shine-Kai Tseng
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L29/42384 , H01L29/7869
摘要： An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.
摘要翻译： 提供了包括源极，漏极，氧化物半导体层，栅极和栅极绝缘体层的有源器件。 源极包括彼此平行的第一条纹电极和与其连接的第一连接电极。 漏极包括彼此平行的第二条状电极和与其连接的第二连接电极，其中第一条形电极和第二条状电极彼此平行，电隔离并交替布置，并且之间形成之字形沟槽。 门沿着之字形沟槽延伸。 氧化物半导体层与源极和漏极接触，其中氧化物半导体层和每个第一条带电极之间的接触面积基本上等于每个第一条带电极的布局面积，并且每个第二条带电极之间的接触面积基本上等于 每个第二条纹电极的布局区域。
-
公开(公告)号：US20120208305A1
公开(公告)日：2012-08-16
申请号：US13454106
申请日：2012-04-24
IPC分类号： H01L33/36
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.
摘要翻译： 提供了一种用于制造像素单元的方法。 在基板上形成TFT。 保护层和图案化的光致抗蚀剂层完全依次形成在基板上。 通过使用图案化的光致抗蚀剂层作为掩模并且部分地去除保护层来形成图案化的保护层，其中图案化的保护层具有位于其侧壁处的底切。形成像素电极材料层以覆盖基板，TFT和 图案化的光致抗蚀剂层，其中电极材料层在底切处断开并暴露底切。 电连接到TFT的像素电极通过剥离图案化的光致抗蚀剂层和覆盖图案化的光致抗蚀剂层的电极材料层的部分同时通过剥离器形成，其中剥离剂从底切渗透到图案化的光致抗蚀剂层和 图案化保护层。
-
公开(公告)号：US20110068345A1
公开(公告)日：2011-03-24
申请号：US12953471
申请日：2010-11-24
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A pixel unit is disposed on a substrate, and the pixel unit includes a thin film transistor (TFT), a patterned protection layer, and a pixel electrode. The TFT is disposed on the substrate. The patterned protection layer is disposed on the TFT. The patterned protection layer is porous and has an undercut located at a sidewall thereof. The pixel electrode is electrically connected to the TFT.
摘要翻译： 像素单元设置在基板上，像素单元包括薄膜晶体管（TFT），图案化保护层和像素电极。 TFT设置在基板上。 图案化保护层设置在TFT上。 图案化保护层是多孔的并且具有位于其侧壁处的底切。 像素电极电连接到TFT。
-
公开(公告)号：US20100258810A1
公开(公告)日：2010-10-14
申请号：US12482433
申请日：2009-06-10
IPC分类号： H01L29/786 , H01L21/336 , H01L29/92 , H01L21/02
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof. A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.
摘要翻译： 提供了一种用于制造像素单元的方法。 在基板上形成TFT。 保护层和图案化的光致抗蚀剂层完全依次形成在基板上。 通过使用图案化的光致抗蚀剂层作为掩模并且部分地去除保护层来形成图案化的保护层，其中图案化的保护层具有位于其侧壁处的底切。 形成像素电极材料层以覆盖衬底，TFT和图案化光致抗蚀剂层，其中电极材料层在底切处断开并暴露底切。 电连接到TFT的像素电极通过剥离图案化的光致抗蚀剂层和覆盖图案化的光致抗蚀剂层的电极材料层的部分同时通过剥离器形成，其中剥离剂从底切渗透到图案化的光致抗蚀剂层和 图案化保护层。
-
公开(公告)号：US08058087B2
公开(公告)日：2011-11-15
申请号：US12356090
申请日：2009-01-20
申请人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
发明人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
IPC分类号： H01L21/338 , H01L31/112
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.
摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。
-
公开(公告)号：US20110070671A1
公开(公告)日：2011-03-24
申请号：US12953472
申请日：2010-11-24
IPC分类号： H01L33/36
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof. A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.
摘要翻译： 提供了一种用于制造像素单元的方法。 在基板上形成TFT。 保护层和图案化的光致抗蚀剂层完全依次形成在基板上。 通过使用图案化的光致抗蚀剂层作为掩模并且部分地去除保护层来形成图案化的保护层，其中图案化的保护层具有位于其侧壁处的底切。 形成像素电极材料层以覆盖衬底，TFT和图案化光致抗蚀剂层，其中电极材料层在底切处断开并暴露底切。 电连接到TFT的像素电极通过剥离图案化的光致抗蚀剂层和覆盖图案化的光致抗蚀剂层的电极材料层的部分同时通过剥离器形成，其中剥离剂从底切渗透到图案化的光致抗蚀剂层和 图案化保护层。
-
公开(公告)号：US20100009481A1
公开(公告)日：2010-01-14
申请号：US12356090
申请日：2009-01-20
申请人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
发明人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.
摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。
-
公开(公告)号：US20120081300A1
公开(公告)日：2012-04-05
申请号：US12970969
申请日：2010-12-17
CPC分类号： G06F3/044 , G06F3/047 , G06F2203/04103 , G06F2203/04111 , G06F2203/04112 , Y10T29/49117
摘要： A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.
摘要翻译： 提供了包括基板，多个第一和第二感测系列以及多个导电修复图案层的触摸面板。 第一感测系列设置在基板上并沿着第一方向延伸。 第一感测系列中的每一个包括多个第一感测焊盘和第一桥接线，并且第一桥接线串联连接两个相邻的第一感测焊盘。 第二感测系列设置在基板上并沿着第二方向延伸。 第二感测系列中的每一个包括多个第二感测焊盘和第二桥接线，并且第二桥接线串联地连接两个相邻的第二感测焊盘。 电浮动的每个导电修复图案层位于第一和第二感测系列的交叉区域周围。 在修复过程完成后，两个相邻的传感垫通过导电修复图案层连接。
-
公开(公告)号：US20110318856A1
公开(公告)日：2011-12-29
申请号：US13225568
申请日：2011-09-06
申请人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
发明人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.
摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。
-
公开(公告)号：US08349631B2
公开(公告)日：2013-01-08
申请号：US13225568
申请日：2011-09-06
申请人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
发明人： Shine-Kai Tseng , Han-Tu Lin , Shiun-Chang Jan , Kuo-Lung Fang
IPC分类号： H01L21/338 , H01L31/112
CPC分类号： H01L27/1248 , H01L27/1288
摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.
摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.014 秒)
