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公开(公告)号：US12133330B2
公开(公告)日：2024-10-29
申请号：US18047348
申请日：2022-10-18
发明人： Akihiro Takeuchi
CPC分类号： H05K1/113 , H05K1/09 , H05K1/181 , H05K2201/0376 , H05K2201/09227 , H05K2201/096 , H05K2201/09736 , H05K2201/10674
摘要： A wiring substrate includes an insulating layer, a pad in a via hole piercing through the insulating layer and exposed at a first surface of the insulating layer, a via conductor on the pad in the via hole, and a wiring part on a second surface of the insulating layer facing away from the first surface. The wiring part is connected to the pad through the via conductor in the via hole.
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公开(公告)号：US20240332109A1
公开(公告)日：2024-10-03
申请号：US18612214
申请日：2024-03-21
发明人： Shinichiro Sekijima
CPC分类号： H01L23/3185 , H01L24/16 , H01L2224/16227 , H01L2924/18161 , H01L2924/3512
摘要： A semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing resin. The semiconductor chip is mounted on the wiring substrate. The sealing resin is filled in a gap between the wiring substrate and the semiconductor chip and extends to an upper surface of the semiconductor chip. The semiconductor chip includes a groove that is formed in an outer peripheral area that is located around a circumference of a predetermined area disposed on the upper surface of the semiconductor chip and that includes a peripheral edge of the upper surface of the semiconductor chip, and that captures an extending portion of the sealing resin extends.
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公开(公告)号：US20240297026A1
公开(公告)日：2024-09-05
申请号：US18590384
申请日：2024-02-28
发明人： Masahiro Sunohara , Riku Nishikawa , Shun Takagi , Sakura Ando
IPC分类号： H01J37/32 , H01L21/683
CPC分类号： H01J37/32724 , H01L21/6833 , H01J2237/334
摘要： A substrate fixing device includes a base plate, a heating portion provided on the base plate, a metal layer provided on the heating portion, and an electrostatic chuck provided on the metal layer. In the substrate fixing device, the metal layer is made of the same material as the base plate.
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公开(公告)号：US20240284593A1
公开(公告)日：2024-08-22
申请号：US18629124
申请日：2024-04-08
发明人： Hikaru Tanaka , Takashi Kasuga
IPC分类号： H05K1/11 , H01L21/48 , H01L23/498 , H05K3/38
CPC分类号： H05K1/113 , H01L21/4857 , H01L23/49822 , H05K3/381
摘要： A wiring substrate includes: a wiring layer; an insulating layer that is laminated on the wiring layer; an opening portion that passes through the insulating layer to the wiring layer; and an electric conductor film that is formed at the opening portion of the insulating layer. A surface of the insulating layer includes a smoothed portion that is not covered by the electric conductor film, and a roughened portion that includes an inner wall surface of the opening portion covered by the electric conductor film and that have surface roughness that is greater than surface roughness of the smoothed portion.
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公开(公告)号：US20240283121A1
公开(公告)日：2024-08-22
申请号：US18436391
申请日：2024-02-08
CPC分类号： H01P3/121 , H01P11/002
摘要： A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.
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公开(公告)号：US20240276653A1
公开(公告)日：2024-08-15
申请号：US18427147
申请日：2024-01-30
发明人： Naohiro Mashino
CPC分类号： H05K3/467 , H05K3/146 , H05K3/4605 , H05K2203/063 , H05K2203/1338
摘要： A wiring board includes a wiring layer, an insulating layer, an oxide thin film, a seed layer, and a conductive layer. The insulating layer is laminated on the wiring layer and includes an opening portion that penetrates until the wiring layer. The oxide thin film is formed on a surface of the insulating layer including an inner wall surface of the opening portion. The seed layer is made of metal and that is laminated on the oxide thin film at a position of the opening portion. The conductive layer is formed on the seed layer. The oxide thin film is a thin film that has a thickness of 1 to 100 angstroms and covers a surface of the insulating layer including the inner wall surface of the opening portion and a surface of the wiring layer exposed from a bottom portion of the opening portion.
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公开(公告)号：US20240247878A1
公开(公告)日：2024-07-25
申请号：US18415723
申请日：2024-01-18
发明人： Yoshihiro Machida
CPC分类号： F28D15/0266 , F28D15/04
摘要： An evaporator includes a first metal layer having a first inner surface and a first outer surface, a second metal layer having a second inner surface bonded to the first inner surface and a second outer surface, and a porous body provided between the first outer surface and the second outer surface. The porous body includes first bottomed holes provided in the first inner surface, second bottomed holes provided in the second inner surface, a fine pore, a first groove portion provided in the first inner surface, and a second groove portion provided in the second inner surface. The first groove portion and the second groove portion are provided not to overlap each other in a plan view. The first outer surface and the second outer surface serve as an outer surface of the evaporator.
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公开(公告)号：US20240215164A1
公开(公告)日：2024-06-27
申请号：US18540013
申请日：2023-12-14
发明人： Kyota YAMAMURA
IPC分类号： H05K1/11 , H01L23/498 , H05K3/10 , H05K3/18 , H05K3/46
CPC分类号： H05K1/113 , H01L23/49822 , H05K3/108 , H05K3/18 , H05K3/4644 , H05K2201/09481 , H05K2201/096 , H05K2203/0723
摘要： A wiring board includes a first interconnect layer, an insulating layer covering the first interconnect layer, a via interconnect penetrating the insulating layer, and a second interconnect layer provided on an upper surface of the insulating layer and electrically connected to the first interconnect layer through the via interconnect. The via interconnect includes a first seed layer that covers an inner wall surface of a via hole penetrating the insulating layer, and an upper surface of the first interconnect layer exposed inside the via hole, and a first electrolytic plating layer provided on the first seed layer. The second interconnect layer includes a second seed layer provided on the upper surface of the insulating layer and on an upper surface of the first electrolytic plating layer, and a second electrolytic plating layer provided on the second seed layer.
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公开(公告)号：US20240155778A1
公开(公告)日：2024-05-09
申请号：US18502605
申请日：2023-11-06
发明人： Akihiro Takeuchi
IPC分类号： H05K3/46
CPC分类号： H05K3/4688 , H05K2201/0212 , H05K2203/0369
摘要： A wiring substrate includes a metal layer, a resin layer, and a wiring structure. The resin layer is laminated on the metal layer. The wiring structure includes a wiring layer and an insulating layer that are laminated on the resin layer, and in which the wiring layer is located by being brought into contact with the resin layer.
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公开(公告)号：US20240155760A1
公开(公告)日：2024-05-09
申请号：US18488140
申请日：2023-10-17
发明人： Yuji YUKIIRI
CPC分类号： H05K1/0271 , H05K1/113 , H05K3/0035 , H05K3/0055 , H05K3/381 , H05K3/429 , H05K2201/0129 , H05K2201/0263 , H05K2203/095
摘要： A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.
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