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    Display device and television system including a self-healing driving circuit
    1.
    发明授权
    Display device and television system including a self-healing driving circuit 有权
    显示装置和电视系统包括自愈式驱动电路

    公开(公告)号：US08416171B2

    公开(公告)日：2013-04-09

    申请号：US12225182

    申请日：2008-05-26

    申请人： Shunichi Murahashi ,  Masafumi Katsutani ,  Hiroaki Fujino ,  Shinsuke Anzai

    发明人： Shunichi Murahashi ,  Masafumi Katsutani ,  Hiroaki Fujino ,  Shinsuke Anzai

    IPC分类号： G09G3/36

    CPC分类号： G09G3/20 ,  G09G3/006 ,  G09G3/3648 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2330/08 ,  G09G2330/12

    摘要： In one embodiment of the present invention, a liquid crystal driving semiconductor IC for driving a display panel includes an output terminal connected to the display panel, an output circuit block including a DAC circuit, and a spare output block including a DAC circuit, the DAC circuits and being connectable to the output terminal. The IC includes an op amp for comparing output signal from the DAC circuit with that of the DAC circuit, and judging circuit for judging, based on the comparison result of the op amp, whether the DAC circuit is defective, and switches and for, if the DAC circuit is defective, connecting the spare DAC circuit to the output terminal in replacement of the defective DAC circuit. This provides an IC for driving a display device, which IC has concrete measures to easily detect a defect in an output circuit, and can perform self-healing for the defect in the output circuit.

    摘要翻译： 在本发明的一个实施例中，用于驱动显示面板的液晶驱动半导体IC包括连接到显示面板的输出端子，包括DAC电路的输出电路块和包括DAC电路的备用输出块，DAC 电路并可连接到输出端子。 IC包括用于比较来自DAC电路的输出信号与DAC电路的输出信号的运算放大器，以及用于基于运算放大器的比较结果判断DAC电路是否有故障的判断电路，以及用于如果 DAC电路有故障，将备用DAC电路连接到输出端子，以代替有缺陷的DAC电路。 这提供了用于驱动显示装置的IC，该IC具有能够容易地检测输出电路中的缺陷的具体措施，并且可以对输出电路中的缺陷执行自愈。

    DRIVE CIRCUIT, DISPLAY DEVICE AND METHOD FOR SELF-DETECTING AND SELF-REPAIRING DRIVE CIRCUIT
    2.
    发明申请
    DRIVE CIRCUIT, DISPLAY DEVICE AND METHOD FOR SELF-DETECTING AND SELF-REPAIRING DRIVE CIRCUIT 审中-公开
    驱动电路，显示装置及自动检测和自动维修电路的方法

    公开(公告)号：US20110254822A1

    公开(公告)日：2011-10-20

    申请号：US13131419

    申请日：2009-11-25

    申请人： Shinsuke Anzai ,  Hiroaki Fujino ,  Masafumi Katsutani

    发明人： Shinsuke Anzai ,  Hiroaki Fujino ,  Masafumi Katsutani

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3688 ,  G09G3/006 ,  G09G2310/027 ,  G09G2330/08

    摘要： A drive circuit (20) of the present invention includes an output circuit block (30), a spare output circuit block (40), a reference output circuit block (41), a comparing and determining circuit (50), and switching circuits (60) and (61). During self-detection, the switching circuit (60) selects one output circuit from the output circuit block (40), disconnects the selected output circuit from a data line of a display panel (80), and connects the spare output circuit block (40) to the data line of the display panel (80). The comparing and determining circuit (50) compares a test output signal from the selected output circuit with a reference output signal from the reference output circuit block (41) and, in accordance with a result of the comparison, determines whether or not the selected output circuit is defective or not. This achieves a drive circuit capable of detecting a failure in an output circuit while driving a display panel without causing a defect in display.

    摘要翻译： 本发明的驱动电路（20）包括输出电路块（30），备用输出电路块（40），参考输出电路块（41），比较和确定电路（50）和开关电路 60）和（61）。 在自检时，开关电路60从输出电路块40选择一个输出电路，将所选择的输出电路与显示面板的数据线断开，并将备用输出电路块40 ）到显示面板（80）的数据线。 比较和确定电路（50）将来自所选择的输出电路的测试输出信号与来自参考输出电路块（41）的参考输出信号进行比较，并且根据比较结果确定所选择的输出 电路有故障。 这实现了能够在驱动显示面板的同时检测输出电路的故障而不引起显示缺陷的驱动电路。

    Semiconductor memory device
    3.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060215468A1

    公开(公告)日：2006-09-28

    申请号：US11378214

    申请日：2006-03-16

    申请人： Shinsuke Anzai ,  Masahiko Watanabe ,  Takahiko Yoshimoto

    发明人： Shinsuke Anzai ,  Masahiko Watanabe ,  Takahiko Yoshimoto

    IPC分类号： G11C7/00

    CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32

    摘要： In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.

    摘要翻译： 在用于以不同定时以时间共享方式读出多电平数据的半导体存储器件中，通过提供用于控制输出缓冲电路的操作定时的多个控制信号线，输出缓冲电路的操作定时可以移位， 可以减少同时工作的输出缓冲电路的数量，从而减少噪声。 此外，通过允许以时间共享的方式早期输出数据的输出缓冲器电路以早期定时运行，数据输出终止，而不会延迟在最后定时操作的输出缓冲电路的操作定时。

    Reading circuit, reference circuit, and semiconductor memory device
    4.
    发明授权
    Reading circuit, reference circuit, and semiconductor memory device 有权
    读取电路，参考电路和半导体存储器件

    公开(公告)号：US06930922B2

    公开(公告)日：2005-08-16

    申请号：US10630568

    申请日：2003-07-29

    申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Shinsuke Anzai ,  Takeshi Nojima

    发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Shinsuke Anzai ,  Takeshi Nojima

    IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28

    CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

    摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

    摘要翻译： 读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。 每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。 包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07301827B2

    公开(公告)日：2007-11-27

    申请号：US11378214

    申请日：2006-03-16

    申请人： Shinsuke Anzai ,  Masahiko Watanabe ,  Takahiko Yoshimoto

    发明人： Shinsuke Anzai ,  Masahiko Watanabe ,  Takahiko Yoshimoto

    IPC分类号： G11C7/00

    CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32

    摘要： In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.

    摘要翻译： 在用于以不同定时以时间共享方式读出多电平数据的半导体存储器件中，通过提供用于控制输出缓冲电路的操作定时的多个控制信号线，输出缓冲电路的操作定时可以移位， 可以减少同时工作的输出缓冲电路的数量，从而减少噪声。 此外，通过允许以时间共享的方式早期输出数据的输出缓冲器电路以早期定时运行，数据输出终止，而不会延迟在最后定时操作的输出缓冲电路的操作定时。

    Bias voltage applying circuit and semiconductor memory device
    9.
    发明授权
    Bias voltage applying circuit and semiconductor memory device 失效
    偏置电压施加电路和半导体存储器件

    公开(公告)号：US07088626B2

    公开(公告)日：2006-08-08

    申请号：US11055641

    申请日：2005-02-09

    申请人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

    发明人： Yasumichi Mori ,  Takahiko Yoshimoto ,  Masahiko Watanabe ,  Shinsuke Anzai ,  Takeshi Nojima ,  Munetaka Masaki

    IPC分类号： G11C7/00

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/063

    摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

    摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。

    Semiconductor integrated circuit
    10.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06661692B2

    公开(公告)日：2003-12-09

    申请号：US10179710

    申请日：2002-06-24

    申请人： Shinsuke Anzai ,  Kenji Kamei ,  Yasumichi Mori

    发明人： Shinsuke Anzai ,  Kenji Kamei ,  Yasumichi Mori

    IPC分类号： G11C506

    CPC分类号： G11C29/80 ,  G11C15/00 ,  G11C15/046 ,  H01L27/0207

    摘要： A semiconductor integrated circuit of the present invention includes: n first output circuits and m second output circuits which are provided such that adjacent first and second output circuits are spaced at a regular first pitch; and input circuits which are provided such that adjacent input circuits are spaced at a regular second pitch, in which the first and second output circuits are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuits and each of the first output circuits is connected to a corresponding one of input circuits by a first conductor line which is kept straight, and second conductor lines are connected to the second output circuits such that each second conductor line passes through a gap between the input circuits.

    摘要翻译： 本发明的半导体集成电路包括：n个第一输出电路和m个第二输出电路，其被设置成使得相邻的第一和第二输出电路以规则的第一间距间隔开; 以及输入电路，其被设置为使得相邻输入电路以规则的第二间距间隔开，其中第一和第二输出电路被设置成使得第一和第二输出电路块中的至少一部分与其他 第一和第二输出电路和第一输出电路中的每一个通过保持直的第一导体线连接到相应的一个输入电路，并且第二导体线连接到第二输出电路，使得每个第二导线通过 通过输入电路之间的间隙。