公开(公告)号：US08667058B2

公开(公告)日：2014-03-04

申请号：US13527311

申请日：2012-06-19

申请人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani

发明人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani

IPC分类号： G06F15/16

CPC分类号： H04L67/1095 ,  H04L67/26 ,  H04L67/325 ,  H04L69/28

摘要： When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.

摘要翻译： 当通过使用传送网络和传送装置向多个用户公开数据时，执行不受用户不利影响的数据公开时间控制，以减少用户之间的数据公开时间的差异。 传送网络系统包括用作数据分发源传送装置的分发服务器和连接到分发目的地用户设备的网络终端。 分发服务器和网络终端均具有时间保持功能和时间同步功能，用于将时间保持功能的时间与主时钟相匹配。 分发服务器预先向网络终端发送披露数据和公开时间。 当网络终端的时间保持功能与公布时间匹配时，网络终端向用户设备发送公开数据。

公开(公告)号：US08456995B2

公开(公告)日：2013-06-04

申请号：US12819862

申请日：2010-06-21

申请人： Kenji Fujihira ,  Takumi Oishi ,  Shinya Fujioka

发明人： Kenji Fujihira ,  Takumi Oishi ,  Shinya Fujioka

IPC分类号： H04L12/28 ,  H04L12/66

CPC分类号： H04L47/10 ,  H04L45/50 ,  H04L47/12 ,  H04L47/2458

摘要： A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.

摘要翻译： 应用本发明的分组传输系统包括：边缘节点，其容纳边缘的接入网;以及核心节点，执行分类从多个边缘节点收集的帧的处理，所述边缘节点提供 标记到从接入网络流入的帧，并且分组传输系统参照标签发送帧。 边缘节点包括根据核心节点的拥塞状态改变提供给从接入网络流入的帧的优先级信息的优先级信息提供部分，以及预先设置为由标签指定的路径的优先级。

公开(公告)号：US20100322072A1

公开(公告)日：2010-12-23

申请号：US12819862

申请日：2010-06-21

申请人： Kenji FUJIHIRA ,  Takumi Oishi ,  Shinya Fujioka

发明人： Kenji FUJIHIRA ,  Takumi Oishi ,  Shinya Fujioka

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L45/50 ,  H04L47/12 ,  H04L47/2458

摘要： A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.

摘要翻译： 应用本发明的分组传输系统包括：边缘节点，其容纳边缘的接入网;以及核心节点，执行分类从多个边缘节点收集的帧的处理，所述边缘节点提供 标记到从接入网络流入的帧，并且分组传输系统参照标签发送帧。 边缘节点包括根据核心节点的拥塞状态改变提供给从接入网络流入的帧的优先级信息的优先级信息提供部分，以及预先设置为由标签指定的路径的优先级。

公开(公告)号：US07652941B2

公开(公告)日：2010-01-26

申请号：US12133890

申请日：2008-06-05

申请人： Kaoru Mori ,  Shinya Fujioka

发明人： Kaoru Mori ,  Shinya Fujioka

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C5/147 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.

摘要翻译： 提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

公开(公告)号：US07570541B2

公开(公告)日：2009-08-04

申请号：US11488024

申请日：2006-07-18

申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

摘要翻译： 字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

公开(公告)号：US20090010080A1

公开(公告)日：2009-01-08

申请号：US12201922

申请日：2008-08-29

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C8/00

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US07394709B2

公开(公告)日：2008-07-01

申请号：US11024734

申请日：2004-12-30

申请人： Kaoru Mori ,  Shinya Fujioka

发明人： Kaoru Mori ,  Shinya Fujioka

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C5/147 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.

摘要翻译： 提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

公开(公告)号：US07239569B2

公开(公告)日：2007-07-03

申请号：US11488785

申请日：2006-07-19

申请人： Shinya Fujioka ,  Kotoku Sato

发明人： Shinya Fujioka ,  Kotoku Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C11/40603 ,  G11C11/40615

摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.

摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。

公开(公告)号：US06868030B2

公开(公告)日：2005-03-15

申请号：US10345373

申请日：2003-01-16

申请人： Yoshiaki Okuyama ,  Shinya Fujioka

发明人： Yoshiaki Okuyama ,  Shinya Fujioka

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C8/16 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C5/025

摘要： A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, different row blocks of the same column block can be accessed via both ports by selectively activating a column line corresponding to a port and another column line corresponding to another port.

摘要翻译： 由核心电路和多个端口构成的双端口半导体存储装置，其核心电路的同一列块中的不同行块同时可访问。 由于每个端口设置有全局数据总线，所以可以通过选择性地激活与端口对应的列线和对应于另一端口的另一列线，通过两个端口来访问同一列块的不同行块。

公开(公告)号：US06759866B2

公开(公告)日：2004-07-06

申请号：US10274602

申请日：2002-10-22

申请人： Katsuhiro Mori ,  Shinya Fujioka

发明人： Katsuhiro Mori ,  Shinya Fujioka

IPC分类号： G01R3128

CPC分类号： G01R31/3004 ,  G01R31/31721

摘要： Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

摘要翻译： 半导体集成电路的工作裕度通过在正常操作模式之间切换电源电路而被可靠地测试，其中第一升压电源用于存储器核心和降压电源，以及测试模式，其中存储器核心 由外部测试电源供电，为测试提供波动的电压，降压电源由第二升压电源供电。