利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.015 秒)

    Solid-state image array with simultaneously activated line drivers
    1.
    发明授权
    Solid-state image array with simultaneously activated line drivers 失效
    具有同时激活的线驱动器的固态图像阵列

    公开(公告)号：US5144447A

    公开(公告)日：1992-09-01

    申请号：US330314

    申请日：1989-03-29

    申请人： Hajime Akimoto ,  Shinya Ohba ,  Mitsuyuki Mitsui

    发明人： Hajime Akimoto ,  Shinya Ohba ,  Mitsuyuki Mitsui

    IPC分类号： H04N5/357 ,  H04N5/3745

    CPC分类号： H04N5/35518 ,  H04N3/1512 ,  H04N3/155

    摘要： The present invention relates to an improved solid-state imaging device having pixel amplifiers. The higher definition of the device results in the increase in number of pixels as large as not less than two million. When a solid-state imaging device having such a large number of pixels is provided with pixel amplifiers, there arise various problems associated with a power source and a power supply line as well as a problem inherent to the pixel amplifier type of solid-state imaging device. The present invention provides a solid-state imaging device in which noises or the like are prevented and a picture or image quality having high definition can be obtained, by suppressing a voltage drop of the power supply line and by compensating fluctuations in outputs of the pixel amplifiers.

    摘要翻译： 本发明涉及具有像素放大器的改进的固态成像装置。 器件的高清晰度导致像素数量的增加不少于200万像素。 当具有这样大量像素的固态成像装置设置有像素放大器时，会出现与电源和电源线相关的各种问题以及像素放大器类型的固态成像固有的问题 设备。 本发明提供一种通过抑制电源线的电压降和补偿像素的输出的波动来防止噪声等的固态成像装置，并且可以获得具有高清晰度的图像或图像质量 放大器

    Solid-state imaging device having series-connected pairs of switching MOS transistors for transferring signal electric charges therethrough
    2.
    发明授权
    Solid-state imaging device having series-connected pairs of switching MOS transistors for transferring signal electric charges therethrough 失效
    固态成像装置具有串联连接的开关MOS晶体管对，用于传送信号电荷

    公开(公告)号：US5016108A

    公开(公告)日：1991-05-14

    申请号：US214514

    申请日：1988-07-01

    申请人： Hajime Akimoto ,  Shinya Ohba

    发明人： Hajime Akimoto ,  Shinya Ohba

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14643

    摘要： A solid-state imaging device has a plurality of light receiving elements formed in a semiconductor substrate. Signal electric charges generated by light incident upon the light receiving elements and stored in the individual light receiving elements are sequentially read out through signal lines by scanning a plurality of switches. Each of the switches includes a series connection of a first MOS transistor switching element formed in the semiconductor substrate and a second MOS transistor formed in a semiconductor provided above the semiconductor substrate through an insulator. The first switching element is disposed on the side of the light receiving element and the second switching element is disposed on the side of the signal output terminal.

    摘要翻译： 固态成像装置具有形成在半导体衬底中的多个光接收元件。 通过扫描多个开关，通过信号线顺序读出入射在光接收元件上并存储在各个光接收元件中的光产生的信号电荷。 每个开关包括通过绝缘体形成在半导体衬底中形成的第一MOS晶体管开关元件和形成在半导体衬底之上的半导体中的第二MOS晶体管的串联连接。 第一开关元件设置在光接收元件的侧面上，第二开关元件设置在信号输出端子的一侧。

    Solid-state imaging device including photoelectric conversion elements integrated at a surface of a semiconductor substrate
    3.
    发明授权
    Solid-state imaging device including photoelectric conversion elements integrated at a surface of a semiconductor substrate 失效
    固态成像装置，其包括集成在半导体基板的表面的光电转换元件

    公开(公告)号：US4954895A

    公开(公告)日：1990-09-04

    申请号：US278844

    申请日：1988-12-02

    申请人： Hajime Akimoto ,  Shinya Ohba

    发明人： Hajime Akimoto ,  Shinya Ohba

    IPC分类号： H01L27/00 ,  H01L27/146 ,  H04N5/335 ,  H04N5/365 ,  H04N5/369 ,  H04N5/374

    CPC分类号： H01L27/14643

    摘要： A solid-state imaging device has a plurality of photodiodes (photoelectric conversion elements) formed in a surface of a semiconductor substrate in a matrix configuration and reading means for reading out signal charges stored in the photodiodes in accordance with the incident lights in a predetermined order. This reading means includes active elements, such as MOS type transistors, connected to each of the photodiodes. A MOS type transistor constituting part of theses active elements is provided in the path of the transmitting incident light for the associated photodiode. By this configuration, the area occupied by one picture element is reduced as far as the processing steps allow.

    摘要翻译： 固态成像装置具有以矩阵形式形成在半导体衬底的表面中的多个光电二极管（光电转换元件）和用于按照预定顺序根据入射光读出存储在光电二极管中的信号电荷的读取装置 。 该读取装置包括连接到每个光电二极管的有源元件，例如MOS型晶体管。 构成这些有源元件的一部分的MOS型晶体管设置在用于相关光电二极管的透射入射光的路径中。 通过该配置，只要处理步骤允许，就减少一个图像元素所占据的面积。

    Digital video signal processor
    4.
    发明授权
    Digital video signal processor 失效
    数字视频信号处理器

    公开(公告)号：US4825287A

    公开(公告)日：1989-04-25

    申请号：US063476

    申请日：1987-06-18

    申请人： Toru Baji ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Shinya Ohba

    发明人： Toru Baji ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Shinya Ohba

    IPC分类号： H04N5/14

    CPC分类号： H04N5/14

    摘要： According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58,000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34,000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19,000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13,000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.

    摘要翻译： 根据本发明，通过进行时间复用处理，可以大大减少信号处理电路等的元件数量。 在具有16个抽头的对称系数的横向滤波器中，例如，现有技术需要约58,000个晶体管。 在使用具有四个抽头功能的四个信号处理核心（即，SPC）的情况下，通过双工处理，所需的晶体管数量可以减少到约34,000个。 在使用具有八个抽头功能的两个SPC的情况下，通过四重处理可将数量减少到约19,000个。 此外，在使用具有十六个抽头功能的一个SPC的情况下，也可以通过八次打印处理将数量减少到约13,000个。 这里，即使SPC的数量减半，元件的数量不减半的原因在于控制电路，存储器等中要使用的元件的数量增加。

    Bulk charge transfer semiconductor device
    6.
    发明授权
    Bulk charge transfer semiconductor device 失效
    大容量充电传输半导体器件

    公开(公告)号：US4032952A

    公开(公告)日：1977-06-28

    申请号：US347426

    申请日：1973-04-03

    申请人： Shinya Ohba ,  Iwao Takemoto ,  Masaharu Kubo

    发明人： Shinya Ohba ,  Iwao Takemoto ,  Masaharu Kubo

    IPC分类号： H01L29/10 ,  H01L29/768 ,  H01L

    CPC分类号： H01L29/7685 ,  H01L29/1062 ,  H01L29/76833 ,  H01L29/76841 ,  Y10S148/08

    摘要： In a charge transfer semiconductor device majority carriers are transferred within a semiconductor body on a substrate from means for introducing majority carriers to means for detecting transferred majority carriers by applying pulsed voltages to a series of electrodes disposed on an insulating layer which is disposed on one surface of the semiconductor body between the introducing means and the detecting means. Depletion regions are formed within the semiconductor body, so that one end of a depletion region below one electrode reaches the substrate and another end of a depletion region below an electrode next to the one electrode does not reach the substrate, whereby majority carriers below the one electrode are pushed out below the next electrode.

    Logic LSI
    7.
    发明授权
    Logic LSI 失效
    逻辑LSI

    公开(公告)号：US5585750A

    公开(公告)日：1996-12-17

    申请号：US478403

    申请日：1995-06-07

    申请人： Kouki Noguchi ,  Kiyokazu Nishioka ,  Shinya Ohba ,  Susumu Narita

    发明人： Kouki Noguchi ,  Kiyokazu Nishioka ,  Shinya Ohba ,  Susumu Narita

    IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  H01L21/82

    CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1217 ,  Y02B60/1282

    摘要： A logic LSI has a plurality of modules such as a CPU contained in one chip. Frequency changing conditions, signals for designating modules whose frequencies are changed for each frequency changing condition, and signals for designating frequencies to be changed are stored in a storage device of a frequency controller, software-wise. The sequentially-input status of the logic LSI is compared with the stored frequency changing conditions and, when the former conforms to the latter, a signal for changing the corresponding frequency is applied to each of the plurality of modules. Each of the modules generates a plurality of internal clocks in synchronization with the basic clock and selects one out of the internal clocks according to the frequency changing signal.

    摘要翻译： 逻辑LSI具有包含在一个芯片中的诸如CPU的多个模块。 频率变化条件，用于为每个频率变化条件改变频率的指定模块的信号和用于指定要改变的频率的信号被存储在频率控制器的存储装置中。 将逻辑LSI的顺序输入状态与存储的频率变化条件进行比较，并且当前者符合后者时，将用于改变相应频率的信号应用于多个模块中的每一个。 每个模块与基本时钟同步地产生多个内部时钟，并根据频率变化信号选择一个内部时钟。

    High speed digital signal processor capable of achieving realtime operation
    8.
    发明授权
    High speed digital signal processor capable of achieving realtime operation 失效
    能实现实时操作的高速数字信号处理器

    公开(公告)号：US4945506A

    公开(公告)日：1990-07-31

    申请号：US324830

    申请日：1989-03-17

    申请人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

    发明人： Toru Baji ,  Hirotsugu Kojima ,  Nario Sumi ,  Yoshimune Hagiwara ,  Shinya Ohba

    IPC分类号： G06F17/10 ,  G06F17/16

    CPC分类号： G06F17/16

    摘要： A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).

    摘要翻译： 一种数字信号处理器，用于在包括多个数据项（x0，x1，x2，...，x7）的列向量输入信号和包括预定数量的系数数据项的矩阵之间计算矢量积，以便产生 列向量输出信号包括多个数据项（y0，y1，y2，...，y7）。 在第一周期中，列向量输入信号的前导数据x0存储在第一存储单元（Rin）中，而在该时间段内，在比第一周期更短的第二周期中，数据项（c0 顺序地读取构成矩阵的第一部分的行方向的c1，c1，c2，...，c7），使得两个数据项被相乘，从而将乘法结果存储在累加器中。 重复执行类似的数据处理，以便基于来自累加器的输出，获得由多个数据项（y0，y1，y2，...，y7）构成的列向量输出信号。