公开(公告)号：US20130228866A1

公开(公告)日：2013-09-05

申请号：US13410207

申请日：2012-03-01

申请人： Tung Ying Lee ,  Wen-Huie Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

发明人： Tung Ying Lee ,  Wen-Huie Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L27/088 ,  G06F17/50 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/66636 ,  H01L29/6681

摘要： Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

摘要翻译： 公开了半导体器件及其制造和设计方法。 在一个实施例中，半导体器件包括设置在包括第一半导体材料的工件上的有源FinFET，所述有源FinFET包括第一鳍片。 非活性FinFET结构设置在靠近有源FinFET的工件上方，该非活性FinFET包括第二鳍片。 第二半导体材料设置在第一鳍片和第二鳍片之间。

公开(公告)号：US20130224952A1

公开(公告)日：2013-08-29

申请号：US13404819

申请日：2012-02-24

申请人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/3205 ,  H01L21/683 ,  H01L21/687 ,  H01L21/31

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

摘要翻译： 提供了一种形成半导体结构的装置和方法。 该装置包括：基板保持件，其保持基板，使得处理表面是弯曲的，例如凸形或凹形。 基板使用点接触保持就位，多个连续接触部分围绕基板延伸，和/或完全围绕基板延伸的连续环。 处理可以包括例如形成源极/漏极区域，沟道区域，硅化物，应力存储层等。

公开(公告)号：US20090206417A1

公开(公告)日：2009-08-20

申请号：US12389315

申请日：2009-02-19

申请人： Shou-Zen Chang ,  HongYu Yu ,  Thomas Y. Hoffman

发明人： Shou-Zen Chang ,  HongYu Yu ,  Thomas Y. Hoffman

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

摘要： A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, a method starts by forming a host dielectric layer over a first and second region of a substrate. A first dielectric capping layer is formed overlying the host dielectric layer on the first and second region and later selectively removed to expose an underlying layer on the first region. A Hf-based dielectric capping layer is formed overlying the underlying layer on the first region and the first dielectric capping layer on the second region. The Hf-based dielectric capping layer is selected to have a healing effect on the exposed surface of the underlying layer on the first region. A control electrode is formed overlaying the Hf-based dielectric capping layer on the first region and on the second region.

摘要翻译： 公开了一种用于制造双功能半导体器件的方法。 在一个方面，一种方法通过在衬底的第一和第二区域上形成主电介质层开始。 形成第一介电覆盖层，覆盖第一和第二区域上的主介电层，然后选择性地去除以暴露第一区域上的下层。 形成Hf基电介质覆盖层，覆盖第一区域上的下层和第二区域上的第一介电覆盖层。 选择Hf基介电覆盖层以对第一区域上的下层的暴露表面具有愈合效果。 在第一区域和第二区域上形成覆盖Hf基电介质覆盖层的控制电极。

公开(公告)号：US20090184376A1

公开(公告)日：2009-07-23

申请号：US12358188

申请日：2009-01-22

申请人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

发明人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

摘要翻译： 公开了一种双功能半导体器件及其制造方法。 一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。 第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。 第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。 第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。 选择金属层以确定第一功函数。 选择第一介电覆盖层以确定第二功函数。

公开(公告)号：US20080136030A1

公开(公告)日：2008-06-12

申请号：US11977027

申请日：2007-10-23

申请人： Shou-Zen Chang ,  Jorge Adrian Kittl ,  HongYu Yu ,  Anne Lauwers ,  Anabela Veloso

发明人： Shou-Zen Chang ,  Jorge Adrian Kittl ,  HongYu Yu ,  Anne Lauwers ,  Anabela Veloso

IPC分类号： H01L23/48 ,  H01L21/425

CPC分类号： H01L21/28097 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2807 ,  H01L21/32155 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

摘要翻译： 提供一种半导体器件，包括与主电极（4）接触的主电极（4）和电介质（3），主电极（4）包括具有功函数的材料和功函数调制元件（6） 用于将主电极（4）的材料的功函数调节到预定值。 主电极（4）还包括用于防止功函数调制元件（6）向电介质（3）和/或电介质（3）扩散的防扩散掺杂剂元件（5）。 还描述了形成这种半导体器件的方法。

公开(公告)号：US20140048888A1

公开(公告)日：2014-02-20

申请号：US13588860

申请日：2012-08-17

申请人： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

发明人： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/02664 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

公开(公告)号：US20130320452A1

公开(公告)日：2013-12-05

申请号：US13486343

申请日：2012-06-01

申请人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

发明人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。

公开(公告)号：US20090283835A1

公开(公告)日：2009-11-19

申请号：US12428341

申请日：2009-04-22

申请人： HongYu Yu ,  Shou-Zen Chang ,  Thomas Y. Hoffmann ,  Philippe Absil

发明人： HongYu Yu ,  Shou-Zen Chang ,  Thomas Y. Hoffmann ,  Philippe Absil

IPC分类号： H01L27/092 ,  H01L21/8234

CPC分类号： H01L21/268 ,  H01L21/28176 ,  H01L21/324 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

摘要翻译： 公开了制造双功能半导体器件的方法及其制造的器件。 在一个方面，所述方法包括在衬底的第二区域中制造第一区域中的第一晶体管和第二晶体管，所述第一晶体管包括第一栅极堆叠，所述第一栅极堆叠层具有第一栅极介电覆盖层和第一栅极电介质覆盖层 金属栅电极层。 第二个栅极堆叠类似于第一个栅极堆叠。 该方法包括将第一热预算应用于第一栅极电介质封盖层，以及将第二热预算应用于第二栅极电介质封盖材料以调节第一和第二栅极堆叠的功函数，第一热预算小于第二热预算 使得在热处理之后，第一和第二栅极堆叠具有不同的功函数。

公开(公告)号：US6121139A

公开(公告)日：2000-09-19

申请号：US106336

申请日：1998-06-29

申请人： Shou-Zen Chang ,  Chaochieh Tsai

发明人： Shou-Zen Chang ,  Chaochieh Tsai

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A titanium based SALICIDE process that is free of bridging effects is described. A controlled quantity of nitrogen is delivered to the silicon oxide (or nitride) surface during titanium silicide formation. The amount of nitrogen is sufficient to inhibit outdiffusion of silicon at the dielectric areas, but insufficient to affect the sheet resistance of the silicon areas. This is accomplished by means of a titanium/titanium-rich titanium nitride/titanium sandwich that is formed in a single sputtering operation. An optional cap layer of stoichiometric titanium nitride may also be added.

摘要翻译： 描述了没有桥接效应的基于钛的SALICIDE工艺。 在硅化钛形成期间将受控量的氮输送到氧化硅（或氮化物）表面。 氮的量足以抑制介电区域硅的扩散，但不足以影响硅区域的薄层电阻。 这通过在单次溅射操作中形成的钛/钛富钛钛/三明治来实现。 还可以加入化学计量的氮化钛的任选的盖层。

公开(公告)号：US20130175578A1

公开(公告)日：2013-07-11

申请号：US13345473

申请日：2012-01-06

申请人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

发明人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L27/088 ,  H01L27/0255 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.