公开(公告)号：US08791519B2

公开(公告)日：2014-07-29

申请号：US12776209

申请日：2010-05-07

Applicant: Jiutao Li ,  Shuang Meng

Inventor： Jiutao Li ,  Shuang Meng

IPC: H01L29/94 ,  H01L27/108 ,  C01G25/02 ,  C01G27/02

CPC classification number: H01L21/02181 ,  C04B35/48 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/31155 ,  H01L21/3143 ,  H01L21/31691 ,  H01L28/40

Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

Abstract translation: 过渡金属氧化物电介质材料掺杂有非金属，以增强金属氧化物的电性能。 在优选实施例中，过渡金属氧化物沉积在底部电极上并注入掺杂剂。 在优选的实施方案中，金属氧化物是氧化铪或氧化锆，掺杂剂是氮。 掺杂剂可将氧化铪或氧化锆的晶体结构转变为四方结构，并增加金属氧化物的介电常数。

公开(公告)号：US08129289B2

公开(公告)日：2012-03-06

申请号：US11543515

申请日：2006-10-05

Applicant: John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

Inventor： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

IPC: H01L21/00

CPC classification number: H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

Abstract translation: 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

公开(公告)号：US08123968B2

公开(公告)日：2012-02-28

申请号：US12042225

申请日：2008-03-04

Applicant: Jingyi Bai ,  Gurtej S Sandhu ,  Shuang Meng

Inventor： Jingyi Bai ,  Gurtej S Sandhu ,  Shuang Meng

IPC: B44C1/22

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0338 ,  H01L21/31612

Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

Abstract translation: 使用两步法将间隔物材料沉积在心轴上进行间距倍增。 第一步的前体与心轴发生最小的反应，形成抵抗第二步骤沉积过程的化学反应的阻挡层，其使用与心轴更具反应性的前体。 在心轴由非晶碳形成并且间隔物材料是氧化硅的情况下，首先通过等离子体增强沉积工艺沉积氧化硅，然后通过热化学气相沉积工艺沉积。 在等离子体增强过程中使用氧气和等离子体增强的四乙基原硅酸盐（TEOS）作为反应物，而在热化学气相沉积工艺中使用臭氧和TEOS作为反应物。 氧气与无定形碳的反应性低于臭氧，从而最小化由无定形碳的氧化引起的心轴的变形。

公开(公告)号：US08119535B2

公开(公告)日：2012-02-21

申请号：US12636581

申请日：2009-12-11

Applicant: Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

Inventor： Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Abstract translation: 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US07279732B2

公开(公告)日：2007-10-09

申请号：US10854593

申请日：2004-05-26

Applicant: Shuang Meng ,  Garo J. Derderian ,  Gurtej Singh Sandhu

Inventor： Shuang Meng ,  Garo J. Derderian ,  Gurtej Singh Sandhu

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L29/511 ,  C23C16/45542 ,  C23C16/515 ,  H01L21/02183 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3141 ,  H01L21/76843 ,  H01L28/75 ,  H01L28/84 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.

Abstract translation: 描述了增加原子层沉积的方法。 在一个实施例中，增强是使用等离子体。 等离子体在将第二前体流入室之前开始。 第二前体与先前的前体反应以在基底上沉积一层。 在一个实施方案中，该层包括来自第一和第二前体中的每一个的至少一种元素。 在一个实施例中，层是TaN。 在一个实施方案中，前体是TaF 5 N和NH 3。 在一个实施例中，等离子体在第一前体的脉冲和第二前体的脉冲之间的吹扫气流期间开始。 在一个实施例中，增强是热能。 在一个实施例中，热能大于ALD（> 300摄氏度）通常接受的热能。 该增强有助于前体在基底上沉积一层的反应。

公开(公告)号：US20070161251A1

公开(公告)日：2007-07-12

申请号：US11681027

申请日：2007-03-01

Applicant: Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

Inventor： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

IPC: H01L21/302

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Abstract translation: 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US20060211260A1

公开(公告)日：2006-09-21

申请号：US11214544

申请日：2005-08-29

Applicant: Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

Inventor： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

IPC: H01L21/31

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Abstract translation: 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US20060003102A1

公开(公告)日：2006-01-05

申请号：US11216897

申请日：2005-08-31

Applicant: Garo Derderian ,  Demetrius Sarigiannis ,  Shuang Meng

Inventor： Garo Derderian ,  Demetrius Sarigiannis ,  Shuang Meng

IPC: C23C16/00

CPC classification number: H01L51/0516 ,  C23C16/40 ,  C23C16/45544 ,  H01L21/3141

Abstract: This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed to form a first species monolayer onto the substrate within the deposition chamber from a gaseous first precursor. The chemisorbed first species is contacted with a gaseous second precursor effective to react with the first species to form an oxide of a component of the first species monolayer. The contacting at least in part results from flowing O3 to the deposition chamber, with the O3 being at a temperature of at least 170° C. at a location where it is emitted into the deposition chamber. The chemisorbing and the contacting are successively repeated to form an oxide comprising layer on the substrate. Additional aspects and implementations are contemplated.

Abstract translation: 本发明包括在衬底上沉积包含层的氧化物的原子层沉积方法。 在一个实施方式中，衬底位于沉积室内。 第一种物质被化学吸附以从气态第一前体在沉积室内的基底上形成第一物质单层。 化学吸附的第一物质与有效与第一物质反应以形成第一物质单层的组分的氧化物的气态第二前体接触。 所述接触至少部分地由流动的O 3至沉积室导致，其中O 3在至少170℃的温度下在其位置处 被排放到沉积室中。 依次重复化学吸附和接触以在基底上形成含氧化物层。 考虑另外的方面和实现。

公开(公告)号：US06943106B1

公开(公告)日：2005-09-13

申请号：US10784074

申请日：2004-02-20

Applicant: Kyle K. Kirby ,  Shuang Meng ,  Garo J. Derderian

Inventor： Kyle K. Kirby ,  Shuang Meng ,  Garo J. Derderian

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/4763 ,  H01L21/44

CPC classification number: C23C16/34 ,  C23C16/45525 ,  C23C18/1608 ,  C23C18/1879 ,  C23C18/36 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.

Abstract translation: 一方面，本发明包括制造用于半导体部件的互连的方法。 提供半导体衬底，并且形成完全贯穿衬底的开口。 第一种材料在小于或等于约200℃的温度下沿着开口的侧壁沉积。沉积可以包括原子层沉积和化学气相沉积中的一个或两个，并且第一材料可以包括金属氮化物。 在第一材料的表面上形成焊料润湿材料。 焊料润湿材料可以包括例如镍。 随后，在开口内和焊料润湿材料之上提供焊料。

公开(公告)号：US08048812B2

公开(公告)日：2011-11-01

申请号：US12769071

申请日：2010-04-28

Applicant: Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

Inventor： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC: H01L21/302

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

Abstract translation: 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一模式的较小特征。 通过图案化无定形碳层来实现间距倍增。 然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。 然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。 将组合图案转移到下面的非晶硅层。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 然后将组合的掩模图案蚀刻到下面的基底中。