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    Circuit board and method for manufaturing thereof
    1.
    发明申请
    Circuit board and method for manufaturing thereof 有权
    电路板及其制造方法

    公开(公告)号：US20080264676A1

    公开(公告)日：2008-10-30

    申请号：US11976207

    申请日：2007-10-22

    申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

    发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

    IPC分类号： H05K1/00

    CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

    摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

    摘要翻译： 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

    Method of manufacturing printed circuit board
    2.
    发明申请
    Method of manufacturing printed circuit board 失效
    制造印刷电路板的方法

    公开(公告)号：US20080261158A1

    公开(公告)日：2008-10-23

    申请号：US12068125

    申请日：2008-02-01

    申请人： Ji-Hong Jo ,  Shuhichi Okabe

    发明人： Ji-Hong Jo ,  Shuhichi Okabe

    IPC分类号： G03F7/20

    CPC分类号： H05K3/205 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0376 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/0117

    摘要： A method of manufacturing a printed circuit board is disclosed. The method includes: forming a relievo pattern and an intaglio pattern on a surface of a base plate; forming a metal plate, which has a metal pattern that corresponds with a shape of the relievo pattern and the intaglio pattern, by plating a surface of the relievo pattern and a surface of the intaglio pattern; separating the metal plate from the base plate; pressing the metal plate onto an insulation layer with the metal pattern facing the insulation layer; and removing a portion of the metal plate such that the metal pattern is exposed. Since this method does not use carriers, there is no need for a chemical etching process for carrier removal.

    摘要翻译： 公开了一种制造印刷电路板的方法。 该方法包括：在基板的表面上形成解除图案和凹版图案; 通过电镀所述消光图案的表面和所述凹版图案的表面，形成金属板，所述金属板具有与所述缓和图案和所述凹版图案的形状相对应的金属图案; 将金属板与基板分离; 将金属板压在绝缘层上，金属图案面向绝缘层; 以及去除所述金属板的一部分以使得所述金属图案露出。 由于该方法不使用载体，因此不需要用于载体去除的化学蚀刻方法。

    Buried pattern substrate and manufacturing method thereof
    3.
    发明申请
    Buried pattern substrate and manufacturing method thereof 审中-公开
    埋地图案基板及其制造方法

    公开(公告)号：US20080009128A1

    公开(公告)日：2008-01-10

    申请号：US11708339

    申请日：2007-02-21

    申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    IPC分类号： H01L21/44

    CPC分类号： H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

    摘要： A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

    摘要翻译： 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

    Method of manufacturing printed circuit board
    4.
    发明授权
    Method of manufacturing printed circuit board 失效
    制造印刷电路板的方法

    公开(公告)号：US07824838B2

    公开(公告)日：2010-11-02

    申请号：US12068125

    申请日：2008-02-01

    申请人： Ji-Hong Jo ,  Shuhichi Okabe

    发明人： Ji-Hong Jo ,  Shuhichi Okabe

    IPC分类号： G03F7/00 ,  G03F7/26 ,  G03F7/40

    CPC分类号： H05K3/205 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0376 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/0117

    摘要： A method of manufacturing a printed circuit board is disclosed. The method includes: forming a relievo pattern and an intaglio pattern on a surface of a base plate; forming a metal plate, which has a metal pattern that corresponds with a shape of the relievo pattern and the intaglio pattern, by plating a surface of the relievo pattern and a surface of the intaglio pattern; separating the metal plate from the base plate; pressing the metal plate onto an insulation layer with the metal pattern facing the insulation layer; and removing a portion of the metal plate such that the metal pattern is exposed. Since this method does not use carriers, there is no need for a chemical etching process for carrier removal.

    摘要翻译： 公开了一种制造印刷电路板的方法。 该方法包括：在基板的表面上形成解除图案和凹版图案; 通过电镀所述消光图案的表面和所述凹版图案的表面，形成金属板，所述金属板具有与所述缓和图案和所述凹版图案的形状相对应的金属图案; 将金属板与基板分离; 将金属板压在绝缘层上，金属图案面向绝缘层; 以及去除所述金属板的一部分以使得所述金属图案露出。 由于该方法不使用载体，因此不需要用于载体去除的化学蚀刻方法。

    Multilayer printed circuit board having a concave metal portion
    6.
    发明授权
    Multilayer printed circuit board having a concave metal portion 失效
    具有凹金属部分的多层印刷电路板

    公开(公告)号：US06184479B2

    公开(公告)日：2001-02-06

    申请号：US08761027

    申请日：1996-12-05

    申请人： Shuhichi Okabe ,  Keizo Sakurai

    发明人： Shuhichi Okabe ,  Keizo Sakurai

    IPC分类号： H01R909

    CPC分类号： H05K1/111 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/4847 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19107 ,  H05K3/0023 ,  H05K3/328 ,  H05K3/4644 ,  H05K2201/09736 ,  Y02P70/611 ,  H01L2924/00014

    摘要： The multilayer printed circuit board includes a substrate, a first conductive circuit layer, a photosensitive dielectric layer and a second conductive circuit layer which is electrically connected to the first conductive circuit layer through photo-via holes formed in the photosensitive dielectric layer. The second conductive circuit layer includes a wiring area where a plurality of wires are arranged and a pad area to which an external wire is to be connected using thermocompression bonding. Significantly, to avoid depressing the photosensitive dielectric layer underneath the pad area during the thermocompression bonding, the thickness of the second conductive circuit layer at least in the pad area, is made greater than that in the wiring area by extending this thickness into the photosensitive dielectric layer.

    摘要翻译： 多层印刷电路板包括基板，第一导电电路层，感光介电层和第二导电电路层，其通过形成在感光介电层中的光通孔与第一导电电路层电连接。 第二导电电路层包括布置多个导线的布线区域和使用热压接将外部布线连接的焊盘区域。 重要的是，为了避免在热压接期间压下焊盘区域下面的感光介电层，至少在焊盘区域中的第二导电电路层的厚度通过将该厚度延伸到光敏电介质中而大于布线区域 层。

    Buried pattern substrate
    8.
    发明申请
    Buried pattern substrate 审中-公开
    埋地图案衬底

    公开(公告)号：US20090242238A1

    公开(公告)日：2009-10-01

    申请号：US12457166

    申请日：2009-06-02

    申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    IPC分类号： H05K1/09

    CPC分类号： H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

    摘要： A buried pattern substrate includes an insulation layer; a circuit pattern buried in the insulation layer such that a part thereof is exposed at a surface of the insulation layer; and a stud bump buried in the insulation layer such that one end portion is exposed at one surface of the insulation layer, and such that the other end portion is exposed at the other surface of the insulation layer.

    摘要翻译： 掩埋图案衬底包括绝缘层; 埋置在绝缘层中的电路图案，使得其一部分在绝缘层的表面露出; 以及埋在所述绝缘层中的螺柱凸起，使得一个端部暴露在所述绝缘层的一个表面处，并且使得所述另一端部暴露在所述绝缘层的另一个表面处。