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18 条记录 (耗时 0.013 秒)

    Forming low-resistance contact to silicon
    2.
    发明授权
    Forming low-resistance contact to silicon 失效
    与硅形成低电阻接触

    公开(公告)号：US4502209A

    公开(公告)日：1985-03-05

    申请号：US528074

    申请日：1983-08-31

    申请人： Moshe Eizenberg ,  Shyam P. Murarka

    发明人： Moshe Eizenberg ,  Shyam P. Murarka

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45 ,  H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002

    摘要： Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum. Reliable low-resistance contacts to VLSI devices are thereby provided in a cost-effective fabrication sequence.Other metallization systems, comprising a silicide and a diffusion barrier to aluminum formed in a single processing step, are also described.

    摘要翻译： 退火沉积在硅上的富含钛的碳化物膜在单个处理步骤中产生在硅化物和随后形成的铝覆盖层之间的稳定的硅化钛接触和碳化钛扩散阻挡层。 因此，以成本有效的制造顺序提供了对VLSI器件的可靠的低电阻触点。 还描述了在单个处理步骤中形成的包括硅化物和对铝的扩散阻挡层的其它金属化系统。

    Silicon rich refractory silicides as gate metal
    6.
    发明授权
    Silicon rich refractory silicides as gate metal 失效
    富硅耐火硅化物作为栅极金属

    公开(公告)号：US4337476A

    公开(公告)日：1982-06-29

    申请号：US178989

    申请日：1980-08-18

    申请人： David B. Fraser ,  Shyam P. Murarka

    发明人： David B. Fraser ,  Shyam P. Murarka

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L23/48

    CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L2924/0002 ,  Y10S148/14

    摘要： Silicon-rich silicides of titanium and tantalum have been found to be suitable for use as the gate metal in semiconductor integrated circuits replacing polysilicon altogether. Such silicon-rich silicides, formed by sintering a cosputtered alloy with silicon to metal ratio of three as in deposited film, are stable even on gate oxide. The use of these compounds leads to stable, low resistivity gates and eliminates the need for the high resistivity polysilicon gate.

    摘要翻译： 已经发现，钛和钽的富含硅的硅化物适合用作半导体集成电路中的栅极金属，从而完全替代多晶硅。 通过烧结沉积膜中硅与金属比为3的共溅射合金形成的这种富硅硅化物即使在栅极氧化物上也是稳定的。 这些化合物的使用导致稳定的低电阻率栅极，并且不需要高电阻率多晶硅栅极。

    Method of fabricating MOS field effect transistors
    7.
    发明授权
    Method of fabricating MOS field effect transistors 失效
    制造MOS场效应晶体管的方法

    公开(公告)号：US4324038A

    公开(公告)日：1982-04-13

    申请号：US209755

    申请日：1980-11-24

    申请人： Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

    发明人： Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/66621 ,  H01L21/28537 ,  H01L29/66643 ,  H01L29/7839

    摘要： A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

    摘要翻译： 在半导体本体（10）中制造MOSFET器件（20）的方法包括在栅极氧化物（10.3）生长之前和形成高电导率表面之后形成源极和漏极接触电极（12.1,12.2）的步骤 地区（10.5）。 每个接触电极（12.1,12.2）的暴露的相互相对的侧壁边缘被涂覆有侧壁二氧化硅层（15.1,15.2），并且将这些侧壁之间的半导体本体（10）的暴露的表面蚀刻到深度 在高导电性表面区域（10.5）之下，以将其分离成源极和漏极区域（10.1,10.2）。 通过使用用于接触电极（12.1,12.2）的肖特基势垒或杂质掺杂材料，可以省略高导电性区域的形成。

    Metallization structures for microelectronic applications and process for forming the structures
    8.
    发明授权
    Metallization structures for microelectronic applications and process for forming the structures 有权
    用于微电子应用的金属化结构和用于形成结构的工艺

    公开(公告)号：US06486533B2

    公开(公告)日：2002-11-26

    申请号：US09990019

    申请日：2001-11-21

    申请人： Ahila Krishnamoorthy ,  David J. Duquette ,  Shyam P. Murarka

    发明人： Ahila Krishnamoorthy ,  David J. Duquette ,  Shyam P. Murarka

    IPC分类号： H01L27082

    CPC分类号： H01L21/76846 ,  C25D3/58 ,  C25D5/18 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

    摘要翻译： 阐述了一种用于微电子电路的金属化结构。 金属化结构包括电介质层，设置在电介质层外部的超薄膜接合层和设置在超薄膜结合层外部的低Me浓度的铜-Me合金层。 Me是铜以外的金属，优选为锌。 Me的浓度小于约5原子％，优选小于约2原子％，甚至更优选小于约1原子％。 在金属化结构的优选实施例中，电介质层，超薄膜结合层和铜-Me合金层都彼此紧邻地设置。 如果需要，可以在上述层序列的外部形成诸如铜膜的主导体。 本发明还考虑了用于形成上述结构的方法以及可用于沉积铜-Me合金层的电镀浴。

    Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide
    9.
    发明授权
    Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide 失效
    使用外延沉积的钴镍化合物与砷化镓的欧姆接触

    公开(公告)号：US5956604A

    公开(公告)日：1999-09-21

    申请号：US889608

    申请日：1997-07-08

    申请人： Sabrina L. Lee ,  Kevin E. Mello ,  Steven R. Soss ,  Toh-Ming Lu ,  Shyam P. Murarka

    发明人： Sabrina L. Lee ,  Kevin E. Mello ,  Steven R. Soss ,  Toh-Ming Lu ,  Shyam P. Murarka

    IPC分类号： C30B23/02 ,  H01L21/285 ,  H01L29/45 ,  H01L21/28

    CPC分类号： H01L29/452 ,  C30B23/02 ,  C30B29/52 ,  H01L21/28575

    摘要： A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.

    摘要翻译： 使用部分离子束（PIB）沉积技术在GaAs（100）衬底14上异质外延沉积CoGe2（001）薄膜。所得到的外延排列是CoGe2（001）GaAs（100）。 获得最佳外延层，其离子能量为1100eV至1200eV，衬底温度为约280℃。 在沉积外延层之前，仅在浸入HF:H2O 1:10中处理衬底晶片。 在这些最佳条件下生长的接触显示欧姆行为，而在更高或更低的底物温度下生长的接触表现出整流行为。 外延形成高熔点，低电阻率的锗化锗相导致与n-GaAs的稳定接触的形成。

    Cobalt silicide metallization for semiconductor integrated circuits
    10.
    发明授权
    Cobalt silicide metallization for semiconductor integrated circuits 失效
    半导体集成电路用硅化钴金属化

    公开(公告)号：US4378628A

    公开(公告)日：1983-04-05

    申请号：US296914

    申请日：1981-08-27

    申请人： Hyman J. Levinstein ,  Shyam P. Murarka ,  Ashok K. Sinha

    发明人： Hyman J. Levinstein ,  Shyam P. Murarka ,  Ashok K. Sinha

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336

    CPC分类号： H01L29/66575 ,  H01L21/28097 ,  H01L21/28518

    摘要： In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2). Subsequently, deposition of an in situ doped layer (33) of polycrystalline silicon (polysilicon) on the cobalt disilicide contacting the monocrystalline silicon portions--followed by gettering, deposition of a layer (34) of aluminum, and standard etch-patterning of the aluminum and polysilicon layers--completes the metallization of the desired MOSFET structures on the silicon wafer.

    摘要翻译： 为了形成MOSFET结构，在具有暴露的多晶（14）或单晶（11）硅部分的图案化半导体晶片上，在约400℃至500℃下沉积并烧结钴层（16），如 以及暴露的氧化物（15或25）部分。 钴与硅部分的暴露表面反应并在其上形成诸如一硅化钴（CoSi）或二钴硅化物（CO 2 Si）或两者的混合物的化合物。 选择性地除去未反应的钴，如通过在合适的酸浴中的选择性蚀刻。 约700℃或更高，优选氧化环境中通常含有约2％氧气的热处理将钴化合物转化成相对稳定的二硅化钴（CoSi 2）。 随后，将多晶硅（多晶硅）的原位掺杂层（33）沉积在与单晶硅部分接触的二硅化钴上，然后吸杂，沉积铝层（34），并且对铝进行标准蚀刻图案化 和多晶硅层 - 完成硅晶片上期望的MOSFET结构的金属化。