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公开(公告)号：US20130173681A1
公开(公告)日：2013-07-04
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译： 提供了利用减少的查找表电路在数据处理装置中执行操作的机制。 输入第一输入值，用于从缩小的查找表电路中选择值的子集。 缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。 值的子集仅包括对应于第一输入值的边界单元值的子集。 输入第二值，并且通过缩小查找表电路对边界单元值子集中的每个边界单元值进行第二值的比较。 缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。
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公开(公告)号：US08131795B2
公开(公告)日：2012-03-06
申请号：US12323257
申请日：2008-11-25
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译： 提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。 改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。 进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。 此外，还使用最小数量的多路复用器来减少多路复用器延迟。
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公开(公告)号：US20100146023A1
公开(公告)日：2010-06-10
申请号：US12331702
申请日：2008-12-10
IPC分类号： G06F7/00
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译： 一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端， 移位器。 检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作， 并行地移动到由最终变速级执行的换档操作以产生转换结果。
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4.发明申请公开(公告)号：US20090077155A1
公开(公告)日：2009-03-19
申请号：US12323257
申请日：2008-11-25
IPC分类号： G06F7/50
CPC分类号： G06F7/483 , G06F7/5443
摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译： 提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。 改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。 进位网络同时执行终结进位功能，并且独立于优化加法器功能的其他所需功能。 此外，还使用最小数量的多路复用器来减少多路复用器延迟。
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5.发明授权Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效具有融合乘法的浮点单元和用浮点单元计算结果的方法公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译： 本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于 操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4） 将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6） 加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8） 其基于前导零的数量和对准偏移量计算指示mo的选择信号 对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。
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公开(公告)号：US07245159B2
公开(公告)日：2007-07-17
申请号：US10891771
申请日：2004-07-15
IPC分类号： H03K19/20
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译： 提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。 因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。 然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。 因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。
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7.发明授权公开(公告)号：US07058830B2
公开(公告)日：2006-06-06
申请号：US10392764
申请日：2003-03-19
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F7/483 , G06F2207/3868 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.
摘要翻译： 本发明提供了一种在浮点单元中节省功率的方法。 旁路逻辑耦合到对准器和乘法器的输入。 对准器旁路耦合到对准器的输出和旁路逻辑的输出。 乘法器旁路耦合到乘法器的输出和旁路逻辑的输出。 对准器旁路和乘法器旁路分别作为对准器旁路信号和乘法器旁路信号的函数传输对准器和乘法器或旁路逻辑的输出。 加法器耦合到对准器旁路和乘法器旁路的输出端。 时钟禁止逻辑用于选择性地启用和禁用对准器，乘法器和旁路逻辑的至少一部分。 这是基于操作和操作数的值完成的。
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公开(公告)号：US08914431B2
公开(公告)日：2014-12-16
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译： 提供了利用减少的查找表电路在数据处理装置中执行操作的机制。 输入第一输入值，用于从缩小的查找表电路中选择值的子集。 缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。 值的子集仅包括对应于第一输入值的边界单元值的子集。 输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。 缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。
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公开(公告)号：US20130173683A1
公开(公告)日：2013-07-04
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
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10.发明授权Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result 有权具有全部和全零检测的移位器，其使用部分移位向量的一部分和平移的移位量以产生移位结果公开(公告)号：US08332453B2
公开(公告)日：2012-12-11
申请号：US12331702
申请日：2008-12-10
IPC分类号： G06F7/00
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译： 一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端， 移位器。 检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作， 并行地移动到由最终变速级执行的换档操作以产生转换结果。
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