公开(公告)号：US20060226552A1

公开(公告)日：2006-10-12

申请号：US11094975

申请日：2005-03-31

申请人： Bailey Jones ,  Sean Lian ,  Simon Molloy

发明人： Bailey Jones ,  Sean Lian ,  Simon Molloy

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L29/66681 ,  H01L21/76816 ,  H01L21/76838 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/7816

摘要： A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of the sacrificial structure; forming at least one opening through the second insulating layer to at least partially expose the sacrificial structure; substantially removing the sacrificial structure, leaving a cavity; and substantially filling the cavity and the at least one opening with a conductive material. The sacrificial structure may be substantially removed by etching the sacrificial structure using an isotropic etchant.

摘要翻译： 在半导体器件中形成掩埋导电结构的方法包括以下步骤：在半导体层上形成第一绝缘层; 在所述第一绝缘层的至少一部分上形成牺牲结构; 在所述牺牲结构的至少一部分上形成第二绝缘层; 通过所述第二绝缘层形成至少一个开口以至少部分地暴露所述牺牲结构; 基本上去除牺牲结构，留下空腔; 并且用导电材料基本上填充空腔和至少一个开口。 可以通过使用各向同性蚀刻剂蚀刻牺牲结构来基本上去除牺牲结构。

公开(公告)号：US20080054481A1

公开(公告)日：2008-03-06

申请号：US11927978

申请日：2007-10-30

申请人： Bailey Jones ,  Sean Lian ,  Simon Molloy

发明人： Bailey Jones ,  Sean Lian ,  Simon Molloy

IPC分类号： H01L23/48

CPC分类号： H01L29/66681 ,  H01L21/76816 ,  H01L21/76838 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/7816

摘要： A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive stricture. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.

摘要翻译： 提供了一种半导体结构，其消除了传统上与一个或多个触点之间的接合和形成在半导体结构中的掩埋导电结构相关联的接触电阻。 半导体结构包括形成在半导体层上的第一绝缘层和形成在第一绝缘层的至少一部分上的导电结构。 在导电狭缝的至少一部分上形成第二绝缘层。 通过第二绝缘层形成至少一个触点并与导电结构电连接。 接触和导电结构在相同的处理步骤中形成为基本均匀的结构。

公开(公告)号：US20060038294A1

公开(公告)日：2006-02-23

申请号：US10919591

申请日：2004-08-17

申请人： John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

发明人： John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

IPC分类号： H01L23/52

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

摘要翻译： 诸如集成电路的器件的金属互连中发生的诸如电迁移和应力诱发迁移的现象通过使用下面的非平面性被抑制。 因此，互连下面的材料形成为具有通常在高度上通常为至少0.02μm的非平坦度，并且有利地在另一个这样的非平面性的100μm之内。 可以预期的是，这种非平面性减少了上覆互连中的晶界运动，伴随着空隙聚集的降低。

公开(公告)号：US06284598B1

公开(公告)日：2001-09-04

申请号：US09447893

申请日：1999-11-23

申请人： Patrick J. Kelley ,  Ranbir Singh ,  Larry B. Fritzinger ,  Cynthia C. Lee ,  John Simon Molloy

发明人： Patrick J. Kelley ,  Ranbir Singh ,  Larry B. Fritzinger ,  Cynthia C. Lee ,  John Simon Molloy

IPC分类号： H01L31336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming round corners for a gate oxide between a floating gate and a control gate of a memory cell comprises the steps of forming the floating gate over a tunnel oxide; forming a mask over the floating gate; forming rounded end caps adjacent distal ends of the mask; transferring the rounding of the end caps to top corners of the floating gate; forming the gate oxide over the floating gate; and, forming the control gate over the gate oxide. A memory cell having a rounded corner interface between the floating gate and control gate is also provided.

摘要翻译： 在存储单元的浮动栅极和控制栅极之间形成用于栅极氧化物的圆角的方法包括在隧道氧化物上形成浮置栅极的步骤; 在浮动门上形成掩模; 在所述掩模的远端附近形成圆形端盖; 将端盖的四舍五入转移到浮动门的顶角; 在浮栅上形成栅极氧化物; 并且在栅极氧化物上形成控制栅极。 还提供了在浮动栅极和控制栅极之间具有圆角接合的存储单元。

公开(公告)号：US06174786B1

公开(公告)日：2001-01-16

申请号：US09447154

申请日：1999-11-23

申请人： Patrick J. Kelley ,  Ranbir Singh ,  Larry B. Fritzinger ,  Cynthia C. Lee ,  John Simon Molloy

发明人： Patrick J. Kelley ,  Ranbir Singh ,  Larry B. Fritzinger ,  Cynthia C. Lee ,  John Simon Molloy

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench. During this process, the rounding of the end caps is transferred to the top corners of a trench.

摘要翻译： 通过在半导体器件中形成沟槽来进行浅沟槽隔离的方法包括以下步骤：形成氧化物层; 形成掩模层; 各向异性地蚀刻掩模层; 形成第二氧化物层; 形成盖层; 在掩模附近形成圆形端盖; 并且将盖的四舍五入转移到沟槽的顶角。 氧化物层形成在半导体器件的衬底上。 掩模层形成在氧化物层的上方。 然后对掩模层进行各向异性蚀刻以形成掩模和掩模中的开口。 掩模中的开口露出衬底，并且开口的宽度大于沟槽的宽度。 蚀刻盖层的毯子形成圆形端盖。 圆形端盖在开口的相对端与掩模相邻，并且端盖之间的距离大约等于沟槽的宽度。 通过等离子体蚀刻沟槽形成沟槽。 在此过程中，端盖的四舍五入转移到沟槽的顶角。