公开(公告)号：US07211872B2

公开(公告)日：2007-05-01

申请号：US09477764

申请日：2000-01-04

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔件内部间隔堆叠和薄的外部间隔件。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06593633B2

公开(公告)日：2003-07-15

申请号：US09477869

申请日：2000-01-05

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06509618B2

公开(公告)日：2003-01-21

申请号：US09476920

申请日：2000-01-04

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06268254B1

公开(公告)日：2001-07-31

申请号：US09458538

申请日：1999-12-09

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

公开(公告)号：US06235598B1

公开(公告)日：2001-05-22

申请号：US09191729

申请日：1998-11-13

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US08854265B1

公开(公告)日：2014-10-07

申请号：US13455085

申请日：2012-04-24

申请人： Simon Yang ,  Keyoor Gosalia

发明人： Simon Yang ,  Keyoor Gosalia

IPC分类号： H01Q1/38

CPC分类号： H01Q9/045

摘要： A microstrip patch antenna including a ground plane base, an L-shaped feed structure and a laminate structure is disclosed herein. A matching network is formed by a clearance member of the laminate structure around a pin and a stub of the L-shaped feed structure on the bottom surface in which the clearance member around the pin effectively decreases shunt inductance and reduces a series capacitance at a feed point to enable a 50 ohm wideband operation.

摘要翻译： 本文公开了包括接地平面基座，L形馈电结构和层叠结构的微带贴片天线。 匹配网络由层叠结构的间隙构件围绕销的底部表面上的L形馈电结构的短截线形成，其中，引脚周围的间隙构件有效地降低了分流电感并减小了馈电时的串联电容 指向启用50欧姆宽带操作。

公开(公告)号：US20120164803A1

公开(公告)日：2012-06-28

申请号：US13413122

申请日：2012-03-06

申请人： JOHN CHEN ,  Simon Yang

发明人： JOHN CHEN ,  Simon Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/77 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A CMOS semiconductor integrated circuit device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.

摘要翻译： CMOS半导体集成电路器件包括NMOS器件，其包括栅极区域，源极区域和漏极区域以及形成在源极区域和漏极区域之间的NMOS沟道区域。 在源极区域内形成碳化硅材料并形成在漏极区域内。 碳化硅材料使得沟道区域处于拉伸模式。 CMOS器件还具有包括栅极区域，源极区域和漏极区域的PMOS器件。 PMOS器件具有形成在源极区域和漏极区域之间的PMOS沟道区域。 源极区内形成硅锗材料，并形成在漏区。 硅锗材料使沟道区域处于压缩模式。

公开(公告)号：US20070072376A1

公开(公告)日：2007-03-29

申请号：US11244955

申请日：2005-10-05

申请人： John Chen ,  Simon Yang

发明人： John Chen ,  Simon Yang

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L21/77 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A CMOS semiconductor integrated circuit device. The CMOS device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.

摘要翻译： CMOS半导体集成电路器件。 CMOS器件包括NMOS器件，其包括栅极区域，源极区域和漏极区域以及形成在源极区域和漏极区域之间的NMOS沟道区域。 在源极区域内形成碳化硅材料并形成在漏极区域内。 碳化硅材料使得沟道区域处于拉伸模式。 CMOS器件还具有包括栅极区域，源极区域和漏极区域的PMOS器件。 PMOS器件具有形成在源极区域和漏极区域之间的PMOS沟道区域。 源极区内形成硅锗材料，并形成在漏区。 硅锗材料使沟道区域处于压缩模式。

公开(公告)号：US06777760B1

公开(公告)日：2004-08-17

申请号：US09477870

申请日：2000-01-05

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J Keating ,  Alan Myers

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06566727B1

公开(公告)日：2003-05-20

申请号：US09433541

申请日：1999-11-03

申请人： Reza Arghavani ,  Robert S. Chau ,  Simon Yang ,  John Graham

发明人： Reza Arghavani ,  Robert S. Chau ,  Simon Yang ,  John Graham

IPC分类号： H01L2500

CPC分类号： H01L21/31053 ,  H01L21/76235

摘要： A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.

摘要翻译： 描述在半导体衬底中形成隔离结构的方法。 首先将沟槽蚀刻到半导体衬底中。 然后用沟槽形成第一氧化物层。 对第一氧化物层进行氮氧化物气氛环境的退火处理，以在第一氧化物层上形成氧氮化物表面，在第一氧化物层和半导体衬底之间形成氮氧化硅界面。 然后将第二氧化物层沉积在第一氧化物层的氧化氮化物表面上。 本发明的方法和隔离结构防止掺杂剂扩散，减小沟槽应力，允许薄栅极氧化物的更均匀生长，并允许使用更薄的栅极氧化物。