公开(公告)号：US07825516B2

公开(公告)日：2010-11-02

申请号：US10316484

申请日：2002-12-11

申请人： Stefanie Ruth Chiras ,  Michael Wayne Lane ,  Sandra Guy Malhotra ,  Fenton Reed Mc Feely ,  Robert Rosenberg ,  Carlos Juan Sambucetti ,  Philippe Mark Vereecken

发明人： Stefanie Ruth Chiras ,  Michael Wayne Lane ,  Sandra Guy Malhotra ,  Fenton Reed Mc Feely ,  Robert Rosenberg ,  Carlos Juan Sambucetti ,  Philippe Mark Vereecken

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

摘要翻译： 集成电路技术; 因此，提供了诸如铜的金属的电迁移和扩散敏感导体以及加工过程，其中在平坦化的化学机械处理的界面表面处，导体金属位于由材料包围的可选低K eff电介质材料的区域中 被选择为防止外扩散，以及在导体金属上形成的膜厚度源和/或用作CoWP封盖的无电选择性沉积的催化层。

公开(公告)号：US07273803B2

公开(公告)日：2007-09-25

申请号：US10724938

申请日：2003-12-01

申请人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

发明人： Yu-Ting Cheng ,  Stefanie Ruth Chiras ,  Donald W. Henderson ,  Sung-Kwon Kang ,  Stephen James Kilpatrick ,  Henry A. Nye, III ,  Carlos J. Sambucetti ,  Da-Yuan Shih

IPC分类号： H01L21/44

CPC分类号： B32B15/01 ,  Y10T428/12528 ,  Y10T428/31681

摘要： A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

摘要翻译： 限球冶金包括基板，在基板上形成的阻挡层，形成在阻挡层上的粘合层，形成在粘合层上的第一可焊层，形成在粘合层上的扩散阻挡层，以及第二可焊接 层形成在扩散阻挡层上。

公开(公告)号：US07084479B2

公开(公告)日：2006-08-01

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

发明人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.