Low friction sheave bracket
    1.
    发明授权

    公开(公告)号:US08827059B2

    公开(公告)日:2014-09-09

    申请号:US13411001

    申请日:2012-03-02

    IPC分类号: B65H75/44 B65H16/02

    摘要: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

    LOW FRICTION SHEAVE BRACKET
    2.
    发明申请
    LOW FRICTION SHEAVE BRACKET 有权
    低摩擦支架

    公开(公告)号:US20130228386A1

    公开(公告)日:2013-09-05

    申请号:US13411001

    申请日:2012-03-02

    IPC分类号: B65H57/14 B60P9/00 B60L9/00

    摘要: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

    摘要翻译: 一种电动采矿车辆,其包括被滚动地支撑在表面上以在表面上移动的框架。 电动机耦合到框架以向车辆提供动力。 电缆电耦合到电动机用于向其供电,并且电缆管理系统耦合到框架并布置成当车辆在表面上移动时接收和支付电缆。 滑轮支架联接到框架并布置成将电缆引导到电缆管理系统中并且包括基本上水平布置的下板,多个垂直辊,其联接到下板并被布置成将电缆引导到电缆 管理系统以及耦合到下板并布置成将电缆提升到下板上方的水平辊。

    PROCESSOR ARCHITECTURE
    3.
    发明申请
    PROCESSOR ARCHITECTURE 有权
    处理器架构

    公开(公告)号:US20120221834A1

    公开(公告)日:2012-08-30

    申请号:US13219321

    申请日:2011-08-26

    IPC分类号: G06F15/76 G06F9/06 G06F9/30

    摘要: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

    摘要翻译: 一种处理器,包括:第一和至少第二数据处理通道,其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数,在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作,并且在使能的条件下,第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

    Resolving metastability
    4.
    发明授权
    Resolving metastability 失效
    解决亚稳态

    公开(公告)号:US07880506B2

    公开(公告)日:2011-02-01

    申请号:US12713412

    申请日:2010-02-26

    申请人: Stephen Felix

    发明人: Stephen Felix

    IPC分类号: H03K19/00

    摘要: A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level.

    摘要翻译: 逻辑电路锁存器,包括用于接收逻辑输入信号的输入级和一对差动放大器,每个差分放大器具有可操作地耦合到输入级的输入,并且它们中的至少一个具有布置成提供锁存器的逻辑输出的输出 。 每个差分放大器包括作为负载连接的晶体管,并且每个差分放大器的输出被耦合以偏置另一个差分放大器的负载晶体管。 如果逻辑输入信号在逻辑电平之间转换时,锁存器从透明状态切换到关闭状态,则如果逻辑输入信号从第一逻辑电平转换到第二逻辑电平,则差分放大器驱动锁存器的逻辑输出,并且 如果输入信号从第二逻辑电平转换到第一逻辑电平,则降低锁存器的逻辑输出。

    BOOTING AN INTEGRATED CIRCUIT
    5.
    发明申请
    BOOTING AN INTEGRATED CIRCUIT 有权
    组装集成电路

    公开(公告)号:US20090172383A1

    公开(公告)日:2009-07-02

    申请号:US12127131

    申请日:2008-05-27

    IPC分类号: G06F15/177 G06F12/02

    CPC分类号: G06F9/441

    摘要: An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

    摘要翻译: 一种集成电路,包括:处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器,所述存储器具有多个区域,每个区域存储用于引导所述处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域,以从所选择的区域检索一个或多个相应的引导属性,并使用一个或多个检索到的引导属性进行引导 。

    Branch prediction combining static and dynamic prediction techniques
    6.
    发明授权
    Branch prediction combining static and dynamic prediction techniques 失效
    分支预测结合静态和动态预测技术

    公开(公告)号:US07404070B1

    公开(公告)日:2008-07-22

    申请号:US09723687

    申请日:2000-11-28

    IPC分类号: G06F9/00

    摘要: A computer system comprises a processor that comprises a hardware branch predictor and software instructions executed by the processor. The software instructions comprise conditional branch instructions and separate static branch prediction instructions. The static branch prediction instructions comprise a plurality of groups of static branch prediction bits, each group being configurable to provide prediction information for a separate conditional branch instruction.

    摘要翻译: 计算机系统包括处理器,其包括由处理器执行的硬件分支预测器和软件指令。 软件指令包括条件分支指令和单独的静态分支预测指令。 静态分支预测指令包括多组静态分支预测比特,每组可配置为单独的条件分支指令提供预测信息。

    Conflict free parallel read access to a bank interleaved branch predictor in a processor
    7.
    发明授权
    Conflict free parallel read access to a bank interleaved branch predictor in a processor 失效
    对处理器中的银行交叉分支预测器进行无冲突的并行读取访问

    公开(公告)号:US07139903B2

    公开(公告)日:2006-11-21

    申请号:US09740419

    申请日:2000-12-19

    IPC分类号: G06F9/42 G06F9/44

    CPC分类号: G06F9/3806 G06F9/3844

    摘要: A computer system has a processor that has a prediction array that avoids conflicts when the prediction array is accessed twice in once clock cycle to retrieve predictions for two separate conditional branch instructions. The prediction array is included as part of a branch prediction logic circuit that includes a bank control logic coupled to the prediction array. The bank control logic assures the conflict noted above is avoided. The prediction array preferably comprises multiple (e.g., 4) single-ported bank memory elements, each bank comprising multiple predictions. The bank control logic uses information associated with a previously fetched and branch predicted conditional branch instruction to generate a bank number for a current branch instruction. The generated bank number corresponds to one of the banks in the prediction array. The processor preferably fetches two (or more) groups (also called “slots”) of instructions each cycle. Each slot may include one or more branch instructions that need to be branch predicted. Thus, the branch prediction logic circuit first generates a bank number for one of the slots and then generates a bank number for the other slot and uses the bank numbers to retrieve predictions from the multi-bank, single ported prediction array. The bank control logic computes the bank numbers in a manner that assures that no two consecutively generated bank numbers are identical.

    摘要翻译: 计算机系统具有处理器,该处理器具有避免冲突的预测阵列,当预测阵列在一个时钟周期中被访问两次以检索对于两个单独的条件分支指令的预测时。 预测阵列被包括作为分支预测逻辑电路的一部分,其包括耦合到预测阵列的组控制逻辑。 银行控制逻辑保证上述冲突得到避免。 预测阵列优选地包括多个(例如,4个)单端口存储体元件,每个存储体包含多个预测。 银行控制逻辑使用与先前提取的和分支预测的条件分支指令相关联的信息来生成当前分支指令的库号。 所生成的库号对应于预测数组中的一个存储体。 处理器优选地每循环取两个(或更多个)指令(也称为“槽”)指令。 每个时隙可以包括需要被分支预测的一个或多个分支指令。 因此,分支预测逻辑电路首先为其中一个时隙产生一个存储体号,然后产生另一时隙的存储体号,并使用存储体号从多存储单端口预测数组中检索预测。 银行控制逻辑以确保没有两个连续生成的银行编号相同的方式计算银行编号。

    Low friction sheave bracket
    8.
    发明授权
    Low friction sheave bracket 有权
    低摩擦轮支架

    公开(公告)号:US08985289B2

    公开(公告)日:2015-03-24

    申请号:US13411001

    申请日:2012-03-02

    IPC分类号: B65H75/44 B65H16/02

    摘要: An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

    摘要翻译: 一种电动采矿车辆,其包括被滚动地支撑在表面上以在表面上移动的框架。 电动机耦合到框架以向车辆提供动力。 电缆电耦合到电动机用于向其提供电力,并且电缆管理系统耦合到框架并布置成当车辆在表面上移动时接收和支付电缆。 滑轮支架联接到框架并布置成将电缆引导到电缆管理系统中并且包括基本上水平布置的下板,多个垂直辊,其联接到下板并被布置成将电缆引导到电缆 管理系统以及耦合到下板并布置成将电缆提升到下板上方的水平辊。

    Receiver interface
    9.
    发明授权
    Receiver interface 有权
    接收器接口

    公开(公告)号:US08509367B2

    公开(公告)日:2013-08-13

    申请号:US12330905

    申请日:2008-12-09

    IPC分类号: H04L7/00

    CPC分类号: H04L7/0008

    摘要: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

    摘要翻译: 本发明提供一种接收机,包括数据输入和选通输入。 当数据信号中的两个连续位相同时,选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级,其被布置为根据恢复的时钟信号对数据信号进行采样,第一采样级包括多个采样电路,并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

    Transmitting a signal from a power amplifier
    10.
    发明授权
    Transmitting a signal from a power amplifier 有权
    从功率放大器发送信号

    公开(公告)号:US08385466B2

    公开(公告)日:2013-02-26

    申请号:US13222471

    申请日:2011-08-31

    IPC分类号: H04K1/02 H04L25/03 H04L25/49

    摘要: A method for limiting peak-to-average power of a signal transmitted from a power amplifier. The method comprises: applying a pulse-shape filter to a first signal, thereby generating a second signal being a filtered version of the first signal; and outputting the second signal for transmission from a power amplifier. The method further comprises: applying each of a plurality of predictor filters to a respective instance of the first signal, each predictor filter approximating the application of the pulse-shape filter to the first signal based on a different respective set of filter coefficients, and each thereby generating a respective third signal. The method also further comprises determining an indicator of amplitude of each of the third signals, selecting the indicator corresponding to the largest of those amplitudes, generating a modifier based on the selected indicator, and using the modifier to limit the first signal prior to applying the pulse-shape filter.

    摘要翻译: 一种用于限制从功率放大器发送的信号的峰值与平均功率的方法。 该方法包括:对第一信号施加脉冲形滤波器,从而产生作为第一信号的滤波版本的第二信号; 并从功率放大器输出用于传输的第二信号。 该方法还包括:将多个预测滤波器中的每一个应用于第一信号的相应实例,每个预测器滤波器基于不同的相应滤波器系数集合逼近脉冲形滤波器对第一信号的应用,并且每个 从而产生相应的第三信号。 该方法还包括确定每个第三信号的幅度指标,选择对应于最大幅度的指示符,基于所选择的指示符生成修改符,并且使用修饰符来限制第一信号, 脉冲形滤波器。