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公开(公告)号：US20080104425A1
公开(公告)日：2008-05-01
申请号：US11555609
申请日：2006-11-01
申请人： Stephen H. Gunther , Edward A. Burton , Stephen H. Gunther , Robert Greiner , Michael Cornaby , Anant Deval , Stephan Jourdan
发明人： Stephen H. Gunther , Edward A. Burton , Stephen H. Gunther , Robert Greiner , Michael Cornaby , Anant Deval , Stephan Jourdan
IPC分类号： G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores
摘要翻译： 两个或多个处理核心的独立功率控制。 更具体地，本发明的至少一个实施例涉及一种将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术
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2.发明申请Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor 审中-公开用于确定在处理器中保持活动的执行单元数量的装置和方法公开(公告)号：US20150241954A1
公开(公告)日：2015-08-27
申请号：US14697553
申请日：2015-04-27
申请人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.
摘要翻译： 描述了在处理器核心中包括多个执行单元的处理器。 处理器还可以包括功率管理电路，以从多个配置中确定具有最低功率成本的配置，每个配置对于相同的主动性能状态具有不同数量的启用的执行单元。 一种方法可以包括：通过处理器的功率管理电路确定来自多个配置的具有最低功率成本的配置，每个配置在处理器的处理器核心中具有不同数量的启用的执行单元，用于相同的主动性能状态。
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3.发明授权Apparatus and method for determining the number of execution cores to keep active in a processor 有权用于确定在处理器中保持活动的执行核心数量的装置和方法公开(公告)号：US09037889B2
公开(公告)日：2015-05-19
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译： 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。
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公开(公告)号：US08996899B2
公开(公告)日：2015-03-31
申请号：US13471222
申请日：2012-05-14
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译： 两个或多个处理核心的独立功率控制。 更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。
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公开(公告)号：US08892861B2
公开(公告)日：2014-11-18
申请号：US13365096
申请日：2012-02-02
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
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公开(公告)号：US08856568B2
公开(公告)日：2014-10-07
申请号：US13486948
申请日：2012-06-01
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译： 两个或多个处理核心的独立功率控制。 更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。
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公开(公告)号：US20140189402A1
公开(公告)日：2014-07-03
申请号：US13729908
申请日：2012-12-28
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3296 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括至少一个处理器核心和功率控制逻辑，其具有能量使用逻辑，以根据第一电压调节器控制模式在低功率周期期间预测处理器和耦合到处理器的电压调节器的能量使用 以及第二电压调节器控制模式，并且至少部分地基于所预测的能量使用来控制所述电压调节器。 描述和要求保护其他实施例。
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公开(公告)号：US20140157021A1
公开(公告)日：2014-06-05
申请号：US13997295
申请日：2012-11-30
申请人： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
发明人： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
摘要： In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。
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公开(公告)号：US20130047007A1
公开(公告)日：2013-02-21
申请号：US13652307
申请日：2012-10-15
申请人： Stephen H. Gunther , Robert J. Greiner , Xia Dia , HUNG-PIAO Ma
发明人： Stephen H. Gunther , Robert J. Greiner , Xia Dia , HUNG-PIAO Ma
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , F04D13/0666 , G05F3/02 , G06F1/20 , G06F2200/201 , G11B33/1413
摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.
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公开(公告)号：US20130013909A1
公开(公告)日：2013-01-10
申请号：US13620119
申请日：2012-09-14
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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