Routing algorithm method for standard-cell and gate-array integrated
circuit design
    1.
    发明授权
    Routing algorithm method for standard-cell and gate-array integrated circuit design 失效
    标准单元和门阵列集成电路设计的路由算法方法

    公开(公告)号:US5483461A

    公开(公告)日:1996-01-09

    申请号:US74961

    申请日:1993-06-10

    CPC classification number: G06F17/5077

    Abstract: An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.

    Abstract translation: 本发明的电子设计自动化工具实施例包括五步骤处理。 在第一步中,对于单元格主机中任意形状的每个引脚主器件,识别引脚访问方向,其中放置通孔的区域将引脚连接到金属层,并且不会导致其他引脚的设计规则违反 - 主人,是物理界限在芯片的表面。 这样的区域被定义为针脚的“通孔区域”。 在第二步骤中,识别每个通孔区域内的至少一个“通孔”,如果将通孔放置在这些点上,则不会违反设计规则。 在第三步骤中,根据它们的通孔将通孔放置在每个单元实例上。 在第四步中,进行“迷宫路由”,以通过金属-1连接相邻的相同的网针。 在第五步中,通过迷宫路由器连接的引脚上的通孔被去除,如果当前网络的连接不完整,则在引脚上仅留下一个通孔。

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