Bit stream aliasing in memory system with probabilistic decoding
    1.
    发明授权
    Bit stream aliasing in memory system with probabilistic decoding 有权
    具有概率解码的存储器系统中的比特流混叠

    公开(公告)号:US08788889B2

    公开(公告)日:2014-07-22

    申请号:US13304272

    申请日:2011-11-23

    摘要: An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.

    摘要翻译: 定义并连接混叠模块以接收要通过数据总线从存储器向存储器的外部控制器发送的第一位流。 将混叠模块定义并连接到第一比特流的别名作为第二比特流,并且通过数据总线传送第二比特流代替第一比特流。 解除混叠模块被定义和连接以在外部控制器处从数据总线接收第二位流。 去混叠模块被定义和连接以将接收到的第二比特流解复用回第一比特流,并将第一比特流提供给外部控制器进行处理。

    Systems and methods of generating a replacement default read threshold
    2.
    发明授权
    Systems and methods of generating a replacement default read threshold 有权
    生成替换默认读取阈值的系统和方法

    公开(公告)号:US08683297B2

    公开(公告)日:2014-03-25

    申请号:US13287299

    申请日:2011-11-02

    IPC分类号: G11C29/00

    CPC分类号: G11C16/26 G11C16/349

    摘要: A method includes generating a replacement default read threshold at least partially based on a default read threshold and on an updated read threshold. The method also includes sending the replacement default read threshold to the memory.

    摘要翻译: 一种方法包括至少部分地基于默认读取阈值和更新的读取阈值来生成替换默认读取阈值。 该方法还包括将替换的默认读取阈值发送到存储器。

    Methods and apparatus for providing fast and power efficient multicast scheme
    3.
    发明授权
    Methods and apparatus for providing fast and power efficient multicast scheme 失效
    提供快速高功率多播方案的方法和装置

    公开(公告)号:US08625484B2

    公开(公告)日:2014-01-07

    申请号:US12365897

    申请日:2009-02-05

    IPC分类号: H04W4/00 H04L1/00

    摘要: A base station (BS) may determine a fixed modulation scheme, a fixed PDU payload size, and a fixed number of PDUs per downlink burst for transmission of multicast data to subscriber stations. The BS may allocate downlink bursts to deliver the multicast data to the subscriber stations via PDUs using the fixed modulation scheme, the fixed PDU payload size, and the fixed number of PDUs per DL burst. A subscriber station (SS) may bypass the processing of multicast frames if the SS does not belong to any multicast groups. An SS may search for multicast connection identifiers (CIDs) in DL MAP IEs in multicast frames if the SS belongs to at least one multicast group. The SS may bypass the parsing of a PDU's MAC header within a corresponding downlink burst in the multicast frame in response to identifying a multicast CID in a DL-MAP IE in a multicast frame.

    摘要翻译: 基站(BS)可以确定固定调制方案,固定PDU有效载荷大小和每个下行链路突发的固定数量的PDU,用于向用户站传输多播数据。 BS可以分配下行链路脉冲串,以使用固定调制方案,固定PDU有效载荷大小和每DL突发的固定数目的PDU,经由PDU向用户站传送多播数据。 如果SS不属于任何多播组,则用户台(SS)可以绕过多播帧的处理。 如果SS属于至少一个多播组,则SS可以在多播帧中的DL MAP IE中搜索多播连接标识符(CID)。 响应于在多播帧中的DL-MAP IE中识别多播CID,SS可以绕过多播帧中的相应下行链路突发中的PDU的MAC报头的解析。

    Memory system with multi-level status signaling and method for operating the same
    4.
    发明授权
    Memory system with multi-level status signaling and method for operating the same 有权
    具有多级状态信号的存储器系统及其操作方法

    公开(公告)号:US08488356B2

    公开(公告)日:2013-07-16

    申请号:US13430548

    申请日:2012-03-26

    申请人: Steven Cheng

    发明人: Steven Cheng

    IPC分类号: G11C5/06

    摘要: A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

    摘要翻译: 存储器系统包括具有电连接到多个存储器芯片中的每一个的相应状态焊盘的公共状态节点的状态电路。 存储器系统还包括设置在状态电路内的多个电阻器,以限定用于在公共状态节点处产生不同电压电平的分压器网络。 每个不同的电压电平指示多个存储器芯片的特定操作状态组合。 此外,多个存储器芯片中的每一个处于第一操作状态或第二操作状态。 此外,不同的电压电平分布在从电源电压电平延伸到参考接地电压电平的电压范围内。

    Bit Stream Aliasing in Memory System with Probabilistic Decoding
    5.
    发明申请
    Bit Stream Aliasing in Memory System with Probabilistic Decoding 有权
    具有概率解码的存储器系统中的比特流混叠

    公开(公告)号:US20130132798A1

    公开(公告)日:2013-05-23

    申请号:US13304272

    申请日:2011-11-23

    IPC分类号: G06F11/10

    摘要: An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.

    摘要翻译: 定义并连接混叠模块以接收要通过数据总线从存储器向存储器的外部控制器发送的第一位流。 将混叠模块定义并连接到第一比特流的别名作为第二比特流,并且通过数据总线传送第二比特流代替第一比特流。 解除混叠模块被定义和连接以在外部控制器处从数据总线接收第二位流。 去混叠模块被定义和连接以将接收到的第二比特流解复用回第一比特流,并将第一比特流提供给外部控制器进行处理。

    METHODS AND SYSTEMS USING DATA RATE DRIVEN PROTOCOL ACCELERATOR FOR MOBILE DEVICES
    7.
    发明申请
    METHODS AND SYSTEMS USING DATA RATE DRIVEN PROTOCOL ACCELERATOR FOR MOBILE DEVICES 失效
    使用数据速率驱动协议加速器进行移动设备的方法和系统

    公开(公告)号:US20100191861A1

    公开(公告)日:2010-07-29

    申请号:US12359106

    申请日:2009-01-23

    IPC分类号: G06F15/16

    CPC分类号: H04L5/0007

    摘要: By controlling whether operations are offloaded to a protocol stack hardware accelerator as a function of data rate, power consumption may be reduced, for example, when data rates result in fragmented or segmented data not suitable for processing by the stack hardware accelerator.

    摘要翻译: 通过控制是否将操作卸载到作为数据速率的函数的协议栈硬件加速器,例如,当数据速率导致不适合于堆栈硬件加速器处理的分段或分段数据时,可能降低功耗。

    METHODS AND APPARATUS FOR FACILITATING DYNAMIC SERVICE-BASED SYSTEM SELECTION AND DETERMINATION
    10.
    发明申请
    METHODS AND APPARATUS FOR FACILITATING DYNAMIC SERVICE-BASED SYSTEM SELECTION AND DETERMINATION 有权
    促进基于动态服务的系统选择和确定的方法和装置

    公开(公告)号:US20100105378A1

    公开(公告)日:2010-04-29

    申请号:US12256882

    申请日:2008-10-23

    IPC分类号: H04W4/00

    摘要: A method for facilitating dynamic service-based system selection and determination may be implemented by a communications device. The method may include presenting system selection options to a user based on information that is received about Network Access Providers (NAPs) and Network Service Providers (NSPs). The method may also include receiving user input about the system selection options. The user may be permitted to provide input about specific services offered by specific NSPs. The method may also include determining user preferences regarding system selection based on the user input. The method may also include creating a preferred roaming list (PRL) based on the user preferences. The method may further include using the PRL to scan for available networks and channels and to find serving systems.

    摘要翻译: 用于促进基于动态服务的系统选择和确定的方法可以由通信设备来实现。 该方法可以包括基于关于网络接入提供商(NAP)和网络服务提供商(NSP)接收的信息向用户呈现系统选择选项。 该方法还可以包括接收关于系统选择选项的用户输入。 可以允许用户提供关于由特定NSP提供的特定服务的输入。 该方法还可以包括基于用户输入来确定关于系统选择的用户偏好。 该方法还可以包括基于用户偏好创建优选漫游列表(PRL)。 该方法还可以包括使用PRL来扫描可用的网络和信道并找到服务系统。