Direct memory access controller
    1.
    发明授权
    Direct memory access controller 有权
    直接内存访问控制器

    公开(公告)号:US09141572B2

    公开(公告)日:2015-09-22

    申请号:US11928132

    申请日:2007-10-30

    IPC分类号: G06F13/28 G06F1/32 G06F13/30

    摘要: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

    摘要翻译: 系统具有至少一个总线,与总线耦合的中央处理单元(CPU),与总线耦合的存储器,具有多个DMA通道的直接存储器访问(DMA)控制器,并且独立于CPU并被耦合 其中,对于访问总线,DMA控制器可以以第一模式被编程以优先于CPU,并且在DMA模式中至少一个DMA通道被暂停以访问总线的第二模式。

    Direct Memory Access Controller
    2.
    发明申请
    Direct Memory Access Controller 有权
    直接内存访问控制器

    公开(公告)号:US20080147907A1

    公开(公告)日:2008-06-19

    申请号:US11928132

    申请日:2007-10-30

    IPC分类号: G06F13/28

    摘要: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

    摘要翻译: 系统具有至少一个总线,与总线耦合的中央处理单元(CPU),与总线耦合的存储器,具有多个DMA通道的直接存储器访问(DMA)控制器,并且独立于CPU并被耦合 其中,对于访问总线,DMA控制器可以以第一模式被编程以优先于CPU,并且在DMA模式中至少一个DMA通道被暂停以访问总线的第二模式。

    Methods and Apparatus for Simulaton of Endovascular and Endoluminal Procedures
    3.
    发明申请
    Methods and Apparatus for Simulaton of Endovascular and Endoluminal Procedures 审中-公开
    血管内和腔内手术模拟方法与装置

    公开(公告)号:US20080020362A1

    公开(公告)日:2008-01-24

    申请号:US11573109

    申请日:2005-08-10

    IPC分类号: G09B23/30

    CPC分类号: G09B23/285 G16H50/50

    摘要: Methods and apparatus provide realistic training in endovascular and endoluminal procedures. One embodiment includes modeling accurately the tubular anatomy of a patient to enable optimized simulation. One embodiment includes simulating the interaction between a flexible device and the anatomy and optimizing the computation. One embodiment includes replicating the functionality of therapeutic devices, e.g. stents, and simulating their interaction with anatomy. One embodiment includes computing hemodynamics inside the vascular model. One embodiment includes reproducing visual feedback, using synthetic X-ray imaging and/or or visible light rendering. One embodiment includes generating contrast agent injection and propagation through a tubular network. One embodiment includes reproducing aspects of the physical environment of an operating room by simulating or tracking, such as C-arm control panel, foot pedals, monitors, real catheters and guidewires, etc. One embodiment includes tracking instrument position and mimicking haptic feedback experienced when manipulating certain medical devices.

    摘要翻译: 方法和手段为血管内和腔内手术提供了现实的训练。 一个实施例包括精确地建模患者的管状解剖结构以实现优化的模拟。 一个实施例包括模拟柔性装置与解剖结构之间的相互作用并优化计算。 一个实施例包括复制治疗装置的功能,例如。 支架,并模拟与解剖学的相互作用。 一个实施例包括计算血管模型内的血液动力学。 一个实施例包括使用合成X射线成像和/或可见光渲染来再现视觉反馈。 一个实施方案包括产生造影剂注射和通过管状网络传播。 一个实施例包括通过模拟或跟踪例如C臂控制面板,脚踏板,监视器,实际导管和导线等来再现手术室的物理环境的方面。一个实施例包括跟踪仪器的位置并模拟所经历的触觉反馈 操纵某些医疗设备。

    MICROCONTROLLER WITH CONFIGURABLE LOGIC ARRAY
    4.
    发明申请
    MICROCONTROLLER WITH CONFIGURABLE LOGIC ARRAY 有权
    具有可配置逻辑阵列的微控制器

    公开(公告)号:US20100122007A1

    公开(公告)日:2010-05-13

    申请号:US12560688

    申请日:2009-09-16

    IPC分类号: G06F13/24

    CPC分类号: G06F13/24

    摘要: A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU.

    摘要翻译: 微控制器可以具有中央处理单元(CPU); 可编程逻辑器件,其接收输入信号并具有与外部引脚耦合的输入/输出;以及中断控制单元,其接收所述内部输入信号中的至少一个或与所述输入/输出中的至少一个耦合,并产生馈送到 CPU。

    Peripheral Supplied Addressing In A Simple DMA
    6.
    发明申请
    Peripheral Supplied Addressing In A Simple DMA 有权
    外围提供的寻址在一个简单的DMA

    公开(公告)号:US20080028110A1

    公开(公告)日:2008-01-31

    申请号:US11736348

    申请日:2007-04-17

    IPC分类号: G06F13/28

    CPC分类号: G06F13/28

    摘要: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

    摘要翻译: 执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

    Surgical training system for laparoscopic procedures
    8.
    发明申请
    Surgical training system for laparoscopic procedures 审中-公开
    腹腔镜手术手术训练系统

    公开(公告)号:US20050142525A1

    公开(公告)日:2005-06-30

    申请号:US10797874

    申请日:2004-03-10

    IPC分类号: G09B23/28

    CPC分类号: G09B23/285

    摘要: A surgical training system includes a tracking system for tracking the position of one or more instruments during a training procedure and objectively evaluating trainee performance based upon one or more metrics using the instrument position information. Instrument position information for the training procedure can be compared against instrument position information for an expert group to generate standardized scores. Various training object can provide realistic haptic feedback during the training procedures.

    摘要翻译: 外科训练系统包括跟踪系统,用于在训练过程期间跟踪一个或多个仪器的位置,并且基于使用仪器位置信息的一个或多个度量来客观地评估受训者的表现。 培训程序的仪器位置信息可以与专家组的仪器位置信息进行比较,以生成标准化分数。 各种训练对象可以在训练过程中提供逼真的触觉反馈。

    Microcontroller with configurable logic array

    公开(公告)号:US09946667B2

    公开(公告)日:2018-04-17

    申请号:US12560688

    申请日:2009-09-16

    IPC分类号: G06F13/24

    CPC分类号: G06F13/24

    摘要: A microcontroller may have a central processing unit (CPU); a programmable logic device receiving input signals and having input/outputs coupled with external pins, and an interrupt control unit receiving at least one of the internal input signals or being coupled with at least one of the input/outputs and generating an interrupt signal fed to the CPU.

    Peripheral supplied addressing in a simple DMA module
    10.
    发明授权
    Peripheral supplied addressing in a simple DMA module 有权
    外设在简单的DMA模块中提供寻址

    公开(公告)号:US07650440B2

    公开(公告)日:2010-01-19

    申请号:US11736348

    申请日:2007-04-17

    IPC分类号: G06F13/28

    CPC分类号: G06F13/28

    摘要: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

    摘要翻译: 执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。