Synaptic weight normalized spiking neuronal networks
    2.
    发明授权
    Synaptic weight normalized spiking neuronal networks 有权
    突触体重标准化的神经元网络

    公开(公告)号:US08655813B2

    公开(公告)日:2014-02-18

    申请号:US12982546

    申请日:2010-12-30

    IPC分类号: G06F15/18 G06N3/08

    CPC分类号: G06N3/049

    摘要: Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.

    摘要翻译: 通过电子突触与突触体重标准化相互联系的神经元网络。 突触权重基于神经元网络的学习规则,使得突触的突触权重决定了刺激源神经元对通过突触连接的目标神经元的影响。 通过对神经网络稳定性执行突触权重归一化,将每个突触重量保持在预定范围内。

    CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY
    3.
    发明申请
    CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY 审中-公开
    经典SPIKING神经网络的空间相关记忆

    公开(公告)号:US20120330872A1

    公开(公告)日:2012-12-27

    申请号:US13598915

    申请日:2012-08-30

    IPC分类号: G06N3/08

    CPC分类号: G06N3/049 G06N3/063 G06N3/08

    摘要: Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.

    摘要翻译: 本发明的实施例涉及用于时空关联记忆的规范加标神经元。 本发明的一个方面提供了包括具有与定向突触连通性的分层神经网络关系的多个电子神经元的时空相关存储器。 多个电子神经元被配置为检测实时数据流中的时空模式的存在,并提取时空模式。 多个电子神经元还被配置为基于学习规则将时空图案存储在多个电子神经元中,并且在呈现时空图案的版本时,检索存储的时空图案。

    SYNAPTIC WEIGHT NORMALIZED SPIKING NEURONAL NETWORKS
    5.
    发明申请
    SYNAPTIC WEIGHT NORMALIZED SPIKING NEURONAL NETWORKS 有权
    SYNAPTIC WEIGHT正规化SPIKING神经网络

    公开(公告)号:US20120173471A1

    公开(公告)日:2012-07-05

    申请号:US12982546

    申请日:2010-12-30

    IPC分类号: G06N3/063 G06N3/08

    CPC分类号: G06N3/049

    摘要: Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.

    摘要翻译: 通过电子突触与突触体重标准化相互联系的神经元网络。 突触权重基于神经元网络的学习规则,使得突触的突触权重决定了刺激源神经元对通过突触连接的目标神经元的影响。 通过对神经网络稳定性执行突触权重归一化,将每个突触重量保持在预定范围内。

    Multi-compartment neurons with neural cores

    公开(公告)号:US09275330B2

    公开(公告)日:2016-03-01

    申请号:US13596278

    申请日:2012-08-28

    摘要: Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.

    SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS
    8.
    发明申请
    SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS 有权
    贝叶斯网络噪声或模型的可伸缩神经硬件

    公开(公告)号:US20150286924A1

    公开(公告)日:2015-10-08

    申请号:US13562187

    申请日:2012-07-30

    摘要: Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.

    摘要翻译: 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路,其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个进入的电子轴突,多个神经模块和将轴突与神经模块相互连接的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。

    Multi-processor cortical simulations with reciprocal connections with shared weights
    9.
    发明授权
    Multi-processor cortical simulations with reciprocal connections with shared weights 有权
    多处理器皮质模拟与共享权重的互惠连接

    公开(公告)号:US08924322B2

    公开(公告)日:2014-12-30

    申请号:US13524798

    申请日:2012-06-15

    IPC分类号: G06N3/00 G06N3/02 G06N3/06

    摘要: Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.

    摘要翻译: 本发明的实施例涉及提供相互通信的分布式仿真框架。 一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组,并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。 每个处理器包括至少一个神经元组。 每个神经元组包括至少一个电子神经元。

    CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY

    公开(公告)号:US20120109863A1

    公开(公告)日:2012-05-03

    申请号:US12828091

    申请日:2010-06-30

    IPC分类号: G06N3/063 G06N3/08

    CPC分类号: G06N3/049 G06N3/063 G06N3/08

    摘要: Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.