公开(公告)号：US08139700B2

公开(公告)日：2012-03-20

申请号：US12492419

申请日：2009-06-26

申请人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

发明人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

IPC分类号： H04L25/00

CPC分类号： H03K5/1565 ,  H03K5/15013 ,  H03K2005/00052

摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。

公开(公告)号：US07460602B2

公开(公告)日：2008-12-02

申请号：US11119505

申请日：2005-04-29

申请人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

发明人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

IPC分类号： H04B3/00

CPC分类号： H04L25/0292 ,  H04L25/03885

摘要： A high speed serial link method is provided, using a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

摘要翻译： 提供了使用数据驱动器和复制驱动器结构的高速串行链路方法，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。

公开(公告)号：US20080120838A1

公开(公告)日：2008-05-29

申请号：US12028439

申请日：2008-02-08

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford ,  Vernon R. Norman

IPC分类号： H01R43/00

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US07368902B2

公开(公告)日：2008-05-06

申请号：US11262101

申请日：2005-10-28

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Vernon R. Norman

IPC分类号： G01R35/00 ,  H03K19/003 ,  G06F19/00

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US07307447B2

公开(公告)日：2007-12-11

申请号：US11263138

申请日：2005-10-27

申请人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Todd M. Rasmus

发明人： Steven M. Clements ,  William P. Cornwell ,  Carrie E. Cox ,  Hayden C. Cranford, Jr. ,  Todd M. Rasmus

IPC分类号： H03K17/16 ,  H03B1/00

CPC分类号： H03K17/164 ,  H03K19/018585 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028

摘要： A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.

摘要翻译： 一种电路设计方法和发射机，其利用分段自串式终止（SSST）发射机的设计来灵活地控制振幅，预加重和转换速率，该发射机具有双重上拉的多个单独可控段的并行配置， 下拉晶体管。 幅度控制，转换速率控制和预加重控制可以通过对各个段的正常或反相输入进行操作/选择来实现。 还提供了一种用于通过调节电源电压来提供/保持跨越自串式端接（SST）发射器的精确输出的机构。 电源电压的调节允许与传统的串行链路接收器终端电压兼容，并在这些电压大于设备的正常供电时保护发射机输出设备。

公开(公告)号：US07187206B2

公开(公告)日：2007-03-06

申请号：US10697514

申请日：2003-10-30

申请人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

发明人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

IPC分类号： H03K19/0175 ,  H03H11/26

CPC分类号： H04L25/028 ,  H03K17/163 ,  H03K17/164

摘要： Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.

摘要翻译： 描述了在串行链路发射机中节省功率的方面。 这些方面包括提供段的并行布置，每个段包括串行链路发射机的预缓冲器和输出级电路，并且每个段独立地使能以实现多个功率电平和多级预加重，同时保持信号中基本恒定的传播延迟 串行链路发射机的路径。 另外的方面包括在预缓冲器级电路中提供旁路路径，以实现段中的可控空闲状态，并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。 还包括在发射机信号路径中提供具有预加重延迟电路的控制元件，以允许预加重延迟电路的最后延迟位的反转，以实现预加重权重的极性改变。

公开(公告)号：US08704583B2

公开(公告)日：2014-04-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03L5/00 ,  H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US20130214865A1

公开(公告)日：2013-08-22

申请号：US13399054

申请日：2012-02-17

申请人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

发明人： John F. Bulzacchelli ,  Steven M. Clements ,  Sergey V. Rylov

IPC分类号： H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45632 ,  H03F2200/27 ,  H03F2203/45631 ,  H03K19/018528

摘要： Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

摘要翻译： 提供电容电平移位电路和方法用于将直流偏移添加到电流积分放大器的输出。 例如，电流积分放大器包括输入放大器级和输出偏移电路。 输入放大器级包括输入节点，第一输出节点和连接在第一输出节点和电源节点之间的第一开关。 输出偏移电路连接到输入放大器级的第一输出节点和电流积分放大器的第二输出节点。 输出偏移电路包括耦合在输入放大器级的第一输出节点和电流积分放大器的第二输出节点之间的第一串联电容器。 输出偏移电路将偏置电压切换到第二输出节点并对第一串联电容器充电，以向电流积分放大器的第二输出节点添加DC偏移。

公开(公告)号：US07769057B2

公开(公告)日：2010-08-03

申请号：US12175846

申请日：2008-07-18

申请人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

发明人： Steven M. Clements ,  Carrie E. Cox ,  Hayden C. Cranford, Jr.

IPC分类号： H04J99/00 ,  H04B3/00

CPC分类号： H04L25/0292 ,  H04L25/03885

摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。

公开(公告)号：US07750744B2

公开(公告)日：2010-07-06

申请号：US12019763

申请日：2008-01-25

申请人： Steven M. Clements ,  Todd M. Rasmus

发明人： Steven M. Clements ,  Todd M. Rasmus

IPC分类号： H03B27/00

CPC分类号： H03L7/0995 ,  H03L7/0891

摘要： A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage.

摘要翻译： 一种用于将单端电荷泵输出连接到差分压控振荡器（VCO）输入的方法，系统和电路装置，以产生来自VCO的低占空比失真。 使用单端电荷泵输出来产生补偿差分电压支路，同时将共模电压电平最佳地对准到当前饥饿环形VCO的接口。 VCO的当前饥饿延迟单元的副本与负反馈一起实现以产生补偿差分电压支路。 单端电荷泵输出耦合到第一晶体管，而第二晶体管耦合到误差放大器的输出端。 误差放大器利用负反馈来偏置第二晶体管，迫使复制电路的输出等于参考电压。