公开(公告)号：US09691684B2

公开(公告)日：2017-06-27

申请号：US14327558

申请日：2014-07-09

Applicant: Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L27/108 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.

公开(公告)号：US09379042B2

公开(公告)日：2016-06-28

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L21/02 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

公开(公告)号：US09142490B2

公开(公告)日：2015-09-22

申请号：US14325335

申请日：2014-07-07

Applicant: Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.

Abstract translation: 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件以及集成电路器件的制造方法。 集成电路装置包括：半导体结构，包括基板和层间绝缘膜，通过基板的TSV结构和层间绝缘膜，基本上包围TSV结构的通孔绝缘膜，以及设置在层间绝缘膜 和通孔绝缘膜。

公开(公告)号：US09018768B2

公开(公告)日：2015-04-28

申请号：US13627790

申请日：2012-09-26

Applicant: Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

Inventor： Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

Abstract translation: 半导体器件包括在衬底的第一表面上的电路图案，覆盖电路图案的绝缘夹层，填充通过绝缘夹层和衬底的通孔的TSV结构，在通孔的内壁上的绝缘层结构 并且在绝缘中间层的上表面上，具有TSV结构和绝缘层结构的缓冲层，通过绝缘层结构的导电结构和电连接到电路图案的绝缘夹层的一部分，接触垫 到TSV结构的底部，以及在第二表面上的保护层结构，以包围接触垫。

公开(公告)号：US20150108605A1

公开(公告)日：2015-04-23

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L23/50 ,  H01L49/02 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

公开(公告)号：US20150102497A1

公开(公告)日：2015-04-16

申请号：US14506930

申请日：2014-10-06

Applicant: Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

Inventor： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

IPC: H01L23/48 ,  H01L23/50 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/00

Abstract: Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

Abstract translation: 提供集成电路（IC）装置，包括：第一多层布线结构，其包括在不同层级并彼此间隔开的基板的第一区域中的多个第一布线层，以及多个第一接触塞 多个第一布线层并连接到多个第一布线层; 贯穿硅通孔（TSV）着陆焊盘，其包括在与所述多个第一布线层中的至少一个第一布线层相同水平的所述基板的第二区域中的第一焊盘层;以及第二焊盘层， 与所述多个第一接触插塞中的至少一个第一接触插塞的水平相同，并接触所述第一衬垫层; TSV着陆板上的第二层多层布线结构; 以及TSV结构，其通过所述基板，并且通过所述TSV着陆焊盘与所述第二多层布线结构连接。

公开(公告)号：US08419853B2

公开(公告)日：2013-04-16

申请号：US12623515

申请日：2009-11-23

Applicant: Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

Inventor： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

IPC: C30B21/04

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Abstract translation: 公开了一种叠层半导体器件及其制造方法。 堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部， 并且上部部分与基板成锥形。 层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

公开(公告)号：US20120142185A1

公开(公告)日：2012-06-07

申请号：US13240040

申请日：2011-09-22

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.

Abstract translation: 在制造半导体器件的方法中，制备具有与第一表面相对的第一表面和第二表面的衬底。 在基板的形成有通孔的区域中形成牺牲层图案。 牺牲层图案在基板的厚度方向上从基板的第一表面延伸。 在衬底的第一表面上形成上部布线层。 上部布线层包括在牺牲层图案上的布线。 部分去除衬底的第二表面以暴露牺牲层图案。 牺牲层图案从基板的第二表面移除以形成露出布线的开口。 通孔形成在开口中以与布线电连接。

公开(公告)号：US20120043666A1

公开(公告)日：2012-02-23

申请号：US13287317

申请日：2011-11-02

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.

Abstract translation: 为了形成半导体器件，通过至少一个电介质层和至少一部分衬底形成通孔结构。 此外，在通孔结构上形成保护缓冲层。 此外，在形成通孔结构和保护缓冲层之后，在衬底上形成用于集成电路的导电结构，其中导电结构不在过孔结构上形成。 因此，导电和通孔结构的劣化被最小化。

公开(公告)号：US20110318922A1

公开(公告)日：2011-12-29

申请号：US13167225

申请日：2011-06-23

Applicant: Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

Inventor： Deok-young Jung ,  Gil-heyun Choi ,  Suk-chul Bang ,  Byung-lyul Park ,  Kwang-jin Moon ,  Dong-chan Lim

IPC: H01L21/283

CPC classification number: H01L21/76802 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/76898

Abstract: The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.

Abstract translation: 所述方法包括通过蚀刻半导体衬底形成半导体衬底图案。 半导体图案具有暴露半导体衬底图案的侧壁的第一通孔，并且由第一通孔露出的半导体衬底图案的侧壁具有杂质层图案。 所述方法还包括处理半导体衬底图案的上表面，所处理的半导体衬底图案的上表面是疏水的; 从由第一通孔露出的半导体衬底图案的侧壁去除杂质层图案; 在由第一通孔露出的半导体衬底图案的侧壁上形成第一绝缘层图案; 以及将第一导电层图案填充到第一通孔中并在第一绝缘层图案之上。