公开(公告)号：US09508425B2

公开(公告)日：2016-11-29

申请号：US13167920

申请日：2011-06-24

申请人： Wei Lu ,  Sung Hyun Jo

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： H01L47/00 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

摘要： A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device.

摘要翻译： 非易失性存储器件结构。 非易失性存储器件结构包括由第一金属材料形成的第一电极，覆盖第一电极的电阻式开关元件。 电阻式开关元件包括以一个或多个缺氧部位为特征的金属氧化物材料。 该器件包括覆盖电阻开关层的第二电极，第二电极由第二金属材料形成。 第二电极由贵金属制成。 当施加到第一电极或第二电极的电压时，使一个或多个缺氧部位从第一电极或第二电极中的一个迁移到另一个电极。 当施加适用于模拟装置的连续电压斜坡时，该装置可以具有连续的电阻变化。 或者，在施加适用于数字设备的连续电压斜坡时，该装置可以具有急剧的电阻变化。

公开(公告)号：US08907317B2

公开(公告)日：2014-12-09

申请号：US13291094

申请日：2011-11-07

申请人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

发明人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

IPC分类号： H01L29/06 ,  H01L21/82 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56 ,  B82Y10/00

CPC分类号： H01L45/1253 ,  B82Y10/00 ,  B82Y30/00 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0071 ,  G11C2213/11 ,  G11C2213/33 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

摘要翻译： 本申请描述了一种交叉开关存储器阵列。 存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。 第一和第二阵列彼此成一角度定向。 阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。 纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

公开(公告)号：US20140036605A1

公开(公告)日：2014-02-06

申请号：US13735814

申请日：2013-01-07

申请人： Wei Lu ,  Sung Hyun Jo

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： G11C13/00 ,  H02H9/08

CPC分类号： H01L45/1616 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/33 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/146 ,  H01L45/148 ,  H02H9/08

摘要： A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

公开(公告)号：US08391049B2

公开(公告)日：2013-03-05

申请号：US12894087

申请日：2010-09-29

申请人： Sung Hyun Jo

发明人： Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： H01L28/20 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/33 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1675

摘要： A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

公开(公告)号：US08274812B2

公开(公告)日：2012-09-25

申请号：US12815369

申请日：2010-06-14

申请人： Hagop Nazarian ,  Sung Hyun Jo

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/15 ,  G11C2213/33

摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

摘要翻译： 一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

公开(公告)号：US20100102290A1

公开(公告)日：2010-04-29

申请号：US12582086

申请日：2009-10-20

申请人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

发明人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

IPC分类号： H01L47/00

CPC分类号： H01L45/1253 ,  B82Y10/00 ,  B82Y30/00 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0071 ,  G11C2213/11 ,  G11C2213/33 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

摘要翻译： 本申请描述了一种交叉开关存储器阵列。 存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。 第一和第二阵列彼此成一角度定向。 阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。 纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

公开(公告)号：US20090014707A1

公开(公告)日：2009-01-15

申请号：US11875541

申请日：2007-10-19

申请人： Wei Lu ,  Sung Hyun Jo

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675

摘要： Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

摘要翻译： 非晶硅非易失性电阻开关器件包括金属电极，非晶硅层和平面掺杂硅电极。 施加到金属电极的电信号将金属离子从金属电极驱动到非晶硅层，以形成从金属电极到平面掺杂硅电极的导电丝，以改变非晶硅层的电阻。 施加到金属电极的另一电信号从非晶硅层去除形成导电丝的至少一些金属离子，以进一步改变非晶硅层的电阻。

公开(公告)号：US09058865B1

公开(公告)日：2015-06-16

申请号：US13525096

申请日：2012-06-15

申请人： Sung Hyun Jo ,  Tanmay Kumar

发明人： Sung Hyun Jo ,  Tanmay Kumar

IPC分类号： G11C13/00

CPC分类号： G11C13/00 ,  G11C11/56 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/33

摘要： A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：提供电阻式开关器件，所述电阻开关器件处于第一状态，其特征在于至少第一电阻，在所述第一状态下向所述电阻开关器件施加第一电压以引起 所述电阻式开关装置改变为第二状态，其中所述第二状态的特征在于至少第二电阻，其中所述第二电阻大于所述第一电阻，并且在所述第二状态下向所述电阻式开关装置施加第二电压以引起 所述电阻性开关器件改变为第三状态，其中所述第三状态的特征在于至少第三电阻，其中所述第二电压具有高于所述第二电压的幅度的幅度，并且其中所述第三电阻大于所述第二电阻 抵抗性。

公开(公告)号：US09012307B2

公开(公告)日：2015-04-21

申请号：US12835704

申请日：2010-07-13

申请人： Sung Hyun Jo ,  Scott Brad Herner

发明人： Sung Hyun Jo ,  Scott Brad Herner

IPC分类号： H01L21/82 ,  H01L21/20 ,  H01L45/00

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/143 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.

摘要翻译： 一种形成两个终端设备的方法。 该方法包括形成覆盖在衬底的表面区域上的第一电介质材料。 底部布线材料形成在第一介电材料上方，并且覆盖在底部布线材料上的开关材料沉积。 对底部布线材料和开关材料进行第一图案化和蚀刻工艺以形成具有顶表面区域和侧面区域的第一结构。 第一结构至少包括底部布线结构和具有第一侧面区域的开关元件和包括开关元件的暴露区域的顶表面区域。 至少形成包括开关元件的暴露区域的第一结构的第二电介质材料。 该方法在第二电介质层的一部分中形成开口区域，以露出开关元件的顶表面区域的一部分。 包括导电材料的顶部布线材料形成为覆盖开口区域，使得导电材料与开关元件直接接触。 执行第二蚀刻工艺以形成至少顶部布线结构。 在具体实施例中，包括开关元件的第一侧区域的第一结构的侧面区域没有来自第二蚀刻工艺的污染物导电材料。

公开(公告)号：US08946046B1

公开(公告)日：2015-02-03

申请号：US13462653

申请日：2012-05-02

申请人： Sung Hyun Jo

发明人： Sung Hyun Jo

IPC分类号： H01L21/20 ,  H01L21/4763 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L21/4763 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

摘要： A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.

摘要翻译： 一种形成非易失性存储器件的方法，包括在衬底上形成第一电极，形成覆盖在第一电极上的电介质层，在电介质层的一部分中形成开口结构，以暴露第一电极的表面， 形成覆盖在电介质层上的电阻性开关材料，并且使用沉积工艺填充至少一部分开口结构，所述电阻开关材料具有由平面区域和缩进结构表征的表面区域，所述凹陷结构覆盖 第一电极，在所述平面区域和所述第一电极之间保持第一厚度的电阻性切换材料，在所述凹陷结构和所述第一电极之间保持电阻性切换材料的第二厚度，其中所述第一厚度大于所述第二厚度， 覆盖电阻式开关材料的第二电极，包括i 结构。