公开(公告)号：US07825495B2

公开(公告)日：2010-11-02

申请号：US12007920

申请日：2008-01-17

Applicant: Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

Inventor： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC: H01L29/06

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Abstract translation: 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。

公开(公告)号：US07732319B2

公开(公告)日：2010-06-08

申请号：US11875713

申请日：2007-10-19

Applicant: Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

Inventor： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract translation: 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20060038291A1

公开(公告)日：2006-02-23

申请号：US11080956

申请日：2005-03-16

Applicant: Hyun-soo Chung ,  Sung-min Sim ,  Myeong-soon Park ,  Dong-hyeon Jang ,  Young-hee Song

Inventor： Hyun-soo Chung ,  Sung-min Sim ,  Myeong-soon Park ,  Dong-hyeon Jang ,  Young-hee Song

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K3/0023 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

Abstract: In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode or a bump electrode, and the semiconductor device may be contained in a wafer level package (WLP) or flip-chip package.

Abstract translation: 在半导体器件的制造中，沉积感光层以覆盖具有感光层的电极的暴露部分。 然后对感光层进行光刻处理，以部分去除覆盖电极的感光层。 电极可以是球形电极或凸块电极，并且半导体器件可以包含在晶片级封装（WLP）或倒装芯片封装中。

公开(公告)号：US20080174025A1

公开(公告)日：2008-07-24

申请号：US12007920

申请日：2008-01-17

Applicant: Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

Inventor： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC: H01L23/488 ,  H01L21/4763

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Abstract translation: 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。

公开(公告)号：US20080036081A1

公开(公告)日：2008-02-14

申请号：US11875713

申请日：2007-10-19

Applicant: Se-Young JEONG ,  Sung-Min SIM ,  Soon-Bum KIM ,  In-Young LEE ,  Young-Hee SONG

Inventor： Se-Young JEONG ,  Sung-Min SIM ,  Soon-Bum KIM ,  In-Young LEE ,  Young-Hee SONG

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract translation: 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，该钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US5840614A

公开(公告)日：1998-11-24

申请号：US744376

申请日：1996-11-07

Applicant: Sung Min Sim ,  Do Yun Hwang

Inventor： Sung Min Sim ,  Do Yun Hwang

IPC: H01L21/301 ,  H01L21/304 ,  H01L21/306 ,  H01L21/68 ,  H01L21/302

CPC classification number: H01L21/6835 ,  H01L21/3043 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A process for producing semiconductor devices using ultraviolet sensitive tape including the steps of forming a plurality of chips on a first surface of a semiconductor wafer, adhering an ultraviolet sensitive tape to the first surface of the semiconductor wafer, back lapping a second surface of the wafer, opposite to the first surface, and irradiating the ultraviolet sensitive tape with ultraviolet rays to release the ultraviolet sensitive tape from the wafer.

Abstract translation: 一种使用紫外线敏感带的半导体器件的制造方法，包括以下步骤：在半导体晶片的第一表面上形成多个芯片，将紫外线敏感带粘附到半导体晶片的第一表面，背面研磨晶片的第二表面 与第一表面相对，并且用紫外线照射紫外线敏感带以从晶片释放紫外线敏感带。

公开(公告)号：US5753532A

公开(公告)日：1998-05-19

申请号：US704996

申请日：1996-08-29

Applicant: Sung Min Sim

Inventor： Sung Min Sim

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/50 ,  H01L21/60

CPC classification number: H01L23/49558 ,  H01L21/565 ,  H01L24/27 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/181

Abstract: A method for manufacturing semiconductor chip package comprising steps of: (a) preparing a lead frame which comprises a pair of opposing side rails which have a plurality of through holes on their upper surface; a die pad onto which a chip will be mounted; a pair of rows of leads, each row being disposed at both sides of the die pad at a distance; and tiebars for mechanically and integrally connecting said die pad to said side rails; (b) filling a resin compound between leads and curing the resin compound to make dambars; (c) attaching said chip to an upper surface of said die pad, and electrically connecting said chip to leads; (d) encapsulating said chip, said die pad, said dambars, a part of said leads and a part of said tiebars to give a package body which is still attached to said lead frame; and (e) cutting said tiebars from lead frame to separate an individual package; and (f) forming leads extending from the package to have an appropriate bend shape is provided.

Abstract translation: 一种制造半导体芯片封装的方法，包括以下步骤：（a）制备引线框架，该引线框架包括在其上表面上具有多个通孔的一对相对的侧轨; 将安装芯片的芯片焊盘; 一排引线，每排以一定距离设置在管芯焊盘的两侧; 以及用于将所述管芯焊盘机械地和一体地连接到所述侧轨的连杆; （b）在引线之间填充树脂化合物并固化树脂化合物以制成堰塞; （c）将所述芯片附接到所述芯片焊盘的上表面，并将所述芯片电连接到引线; （d）封装所述芯片，所述芯片焊盘，所述绝缘体，所述引线的一部分和所述拉杆的一部分，以给出仍然附接到所述引线框架的封装体; 和（e）从引线框架切割所述拉杆以分离单独的包装; 和（f）形成从封装延伸以具有适当的弯曲形状的引线。

公开(公告)号：US5543493A

公开(公告)日：1996-08-06

申请号：US280769

申请日：1994-07-26

Applicant: Chan-eon Park ,  Hwang-kyu Yun ,  Sung-min Sim ,  Wan-gyun Choi

Inventor： Chan-eon Park ,  Hwang-kyu Yun ,  Sung-min Sim ,  Wan-gyun Choi

IPC: C08G73/10 ,  C08J7/12 ,  C08L79/08 ,  H01L21/312 ,  B05D3/10

CPC classification number: C08J7/12 ,  C08L79/08 ,  C08J2379/08

Abstract: A method for treating a polyimide surface which includes the steps of amine-treating the polyimide surface and drying the thusly amine-treated polyimide surface. The amine-treating step is preferably carried out by immersing the polyimide in an amine solution which includes an amine and a solvent. The amine is preferably an aliphatic, aromatic, or siloxane amine. The drying step is preferably carried out a temperature of about 50.degree.-200.degree. C. The polyimide is preferably a polyimide having at least one imide functional group in its main chain, and is most preferably a polycondensate of at least one dianhydride and at least one diamine.

Abstract translation: 一种处理聚酰亚胺表面的方法，包括胺处理聚酰亚胺表面并干燥胺处理的聚酰亚胺表面的步骤。 胺处理步骤优选通过将聚酰亚胺浸入包括胺和溶剂的胺溶液中来进行。 胺优选为脂族，芳族或硅氧烷胺。 干燥步骤优选在约-50℃〜200℃的温度下进行。聚酰亚胺优选为主链中具有至少一个酰亚胺官能团的聚酰亚胺，最优选为至少一种二酐的缩聚物，至少 一个二胺。

公开(公告)号：US07524763B2

公开(公告)日：2009-04-28

申请号：US11145994

申请日：2005-06-07

Applicant: Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

Inventor： Soon-Bum Kim ,  Ung-Kwang Kim ,  Keum-Hee Ma ,  Young-Hee Song ,  Sung-Min Sim ,  Se-Yong Oh ,  Kang-Wook Lee ,  Se-Young Jeong

IPC: H01L21/44

CPC classification number: C25D7/12 ,  C25D5/02 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

Abstract translation: 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。