利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.023 秒)

    Semiconductor devices comprising a plurality of gate structures
    2.
    发明授权
    Semiconductor devices comprising a plurality of gate structures 有权
    包括多个栅极结构的半导体器件

    公开(公告)号：US08362542B2

    公开(公告)日：2013-01-29

    申请号：US12847351

    申请日：2010-07-30

    申请人： Dae-Woong Kang ,  Sung-Nam Chang ,  Jin-Joo Kim ,  Kyong-Joo Lee ,  Eun-Jung Lee

    发明人： Dae-Woong Kang ,  Sung-Nam Chang ,  Jin-Joo Kim ,  Kyong-Joo Lee ,  Eun-Jung Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L21/76 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.

    摘要翻译： 提供包括设置在半导体衬底上的多个栅极结构的半导体器件。 栅极结构中的每一个包括隧道介电层，浮置栅极，栅极间介电层，控制栅极和掩模层。 衬套覆盖相邻浮动门的相对侧壁。 间隔件设置在衬垫上，间隔件从相邻栅极结构的相对侧壁突出，并且每个间隔件的顶部设置在相应的一个栅极结构的顶部的下方。 衬垫限定相应空气间隙的侧壁，间隔件限定相应气隙的顶部。

    Method of forming semiconductor device
    3.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US07736989B2

    公开(公告)日：2010-06-15

    申请号：US12176618

    申请日：2008-07-21

    申请人： Dong-Won Chang ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

    发明人： Dong-Won Chang ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

    IPC分类号： H01L21/762 ,  H01L21/28

    CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L27/11524

    摘要： A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.

    摘要翻译： 一种形成半导体器件的方法，其中所述方法可以包括在半导体衬底中形成第一沟槽，形成填充第一沟槽的第一器件隔离图案，在第一器件隔离图案的侧壁上形成间隔物，在第二沟槽中形成第二沟槽 半导体衬底在第一器件隔离图案之间，以及形成填充第二沟槽的第二器件隔离图案。 使用采用第一器件隔离图案和间隔物作为掩模的蚀刻工艺形成第二沟槽。

    Non-volatile memory devices and methods of forming non-volatile memory devices
    5.
    发明申请
    Non-volatile memory devices and methods of forming non-volatile memory devices 失效
    非易失性存储器件和形成非易失性存储器件的方法

    公开(公告)号：US20070034938A1

    公开(公告)日：2007-02-15

    申请号：US11443449

    申请日：2006-05-31

    申请人： Dae-woong Kang ,  Sung-nam Chang ,  Kwang-jae Lee

    发明人： Dae-woong Kang ,  Sung-nam Chang ,  Kwang-jae Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

    摘要： A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively remove etch byproducts. An oxidation process may be performed to cure etch damage of an intergate dielectric pattern, a floating gate and a gate insulator. The barrier spacer and/or the oxidation process enable a non-volatile memory device having enhanced speed and reliability to be formed.

    摘要翻译： 包括用于保护包括金属层的控制栅极免受可能由于暴露于清洁溶液和/或氧气造成的损害的阻挡间隔物的非易失性存储器件。 使用隔离间隔层，可以使用使用大功率清洗溶液的清洁方法来有效地去除蚀刻副产物。 可以执行氧化过程以固化隔间电介质图案，浮动栅极和栅极绝缘体的蚀刻损伤。 隔离间隔物和/或氧化过程使得能够形成具有增强的速度和可靠性的非易失性存储器件。

    Non-volatile memory devices and methods of fabricating the same
    7.
    发明申请
    Non-volatile memory devices and methods of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20050164457A1

    公开(公告)日：2005-07-28

    申请号：US11086161

    申请日：2005-03-21

    申请人： Dong-Chan Kim ,  Sung-Nam Chang

    发明人： Dong-Chan Kim ,  Sung-Nam Chang

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Non-volatile memory devices and fabrication methods thereof are provided. The device includes a plurality of isolation layers formed at a semiconductor device, a plurality of stacked gates crossing over an active region between the isolation layers, and an oxidation barrier layer covering the stacked gate. Each of the stacked gates has a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the control gate electrode and the floating gate. Also, the inter-gate dielectric layer has a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked. The oxidation barrier layer is formed prior to a subsequent thermal oxidation process for curing etch damage that occurs during formation of the stacked gates.

    摘要翻译： 提供非易失性存储器件及其制造方法。 该器件包括形成在半导体器件上的多个隔离层，跨过隔离层之间的有源区域的多个层叠栅极和覆盖堆叠栅极的氧化阻挡层。 层叠栅极中的每一个具有跨越有源区域的控制栅极电极，插入在控制栅电极和有源区域之间的浮置栅极以及介于控制栅极电极和浮置栅极之间的栅极间电介质层。 此外，栅极间电介质层具有依次层叠的底部电介质层，中间电介质层和顶部电介质层。 在随后的热氧化过程之前形成氧化阻挡层，用于固化在层叠栅极形成期间发生的蚀刻损伤。

    Flash memory device and method of making same
    8.
    发明授权
    Flash memory device and method of making same 失效

    公开(公告)号：US06515329B2

    公开(公告)日：2003-02-04

    申请号：US10068483

    申请日：2002-02-05

    申请人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    发明人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.