公开(公告)号：US08907416B2

公开(公告)日：2014-12-09

申请号：US13780579

申请日：2013-02-28

申请人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

发明人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

摘要翻译： 公开了半导体器件和制造方法。 该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。 第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。 第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。 终端结构围绕第一和第二栅极流道和有源区域。 端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

公开(公告)号：US08536646B2

公开(公告)日：2013-09-17

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US08524558B2

公开(公告)日：2013-09-03

申请号：US13200882

申请日：2011-10-04

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08507362B2

公开(公告)日：2013-08-13

申请号：US13115097

申请日：2011-05-24

申请人： Tao Feng ,  Sung-Shan Tai

发明人： Tao Feng ,  Sung-Shan Tai

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/02035 ,  H01L21/02013 ,  H01L21/3043 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

公开(公告)号：US08372708B2

公开(公告)日：2013-02-12

申请号：US13200869

申请日：2011-10-04

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

IPC分类号： H01L21/8238 ,  H01L21/425

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US20130001699A1

公开(公告)日：2013-01-03

申请号：US13171475

申请日：2011-06-29

申请人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

发明人： Sung-Shan Tai ,  Po-Hsien Li ,  Guo-Liang Yang ,  Shian Hau Liao

IPC分类号： H01L27/06 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L29/872

摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.

摘要翻译： 本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。 肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。 本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸 在两个沟槽之间的间距。

公开(公告)号：US08252647B2

公开(公告)日：2012-08-28

申请号：US12551417

申请日：2009-08-31

申请人： Yeeheng Lee ,  Sung-Shan Tai ,  Hong Chang ,  John Chen

发明人： Yeeheng Lee ,  Sung-Shan Tai ,  Hong Chang ,  John Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66719 ,  H01L29/66734

摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

摘要翻译： 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

公开(公告)号：US20120193631A1

公开(公告)日：2012-08-02

申请号：US13431551

申请日：2012-03-27

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20120098059A1

公开(公告)日：2012-04-26

申请号：US13343666

申请日：2012-01-04

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上方形成由绝缘体隔开的第二导电材料。 在沟槽上形成第一绝缘体层。 在衬底中形成体层。 源体形成在体层中。 在沟槽和源极上形成第二绝缘体层。 源极和栅极触点通过第二绝缘体层形成。 在第二绝缘体层上形成源极和栅极金属。 提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08058687B2

公开(公告)日：2011-11-15

申请号：US11700688

申请日：2007-01-30

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。