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公开(公告)号：US20250072299A1
公开(公告)日：2025-02-27
申请号：US18454931
申请日：2023-08-24
Inventor： Che-Hao CHANG , Jiun-Yun LI , Yu-Cheng LI , Yu-Jul WU
Abstract: An electronic device includes a substrate, a hyperbolic magnet, a pair of depletion gates, a pair of barrier gates and a accumulation gate. The hyperbolic magnet is over the substrate and has a first magnet portion and a second magnet portion separated from each other. The first magnet portion and the second magnet portion have a first convex surface and a second convex surface facing the first convex surface, respectively. The depletion gates are separated from each other and between the first convex surface and the second convex surface over the substrate. The barrier gates are between the depletion gates. The accumulation gate is over the depletion gates and between the barrier gates.
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公开(公告)号：US20250072143A1
公开(公告)日：2025-02-27
申请号：US18938484
申请日：2024-11-06
Inventor： Li-Wen HUANG , Chung-Liang CHENG , Ping-Hao LIN , Kuo-Cheng LEE
IPC: H01L27/146
Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
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公开(公告)号：US20250072099A1
公开(公告)日：2025-02-27
申请号：US18455211
申请日：2023-08-24
Inventor： Kuei-Yu Kao , Chiung-Yu Cho , Ming-Ching Chang
IPC: H01L21/8234 , H01L21/311 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: Provided are devices and methods for forming devices. A method includes forming structures over a substrate; forming a layer between the structures; performing a first etch process to recess the layer to a surface having a serrated profile; optionally forming a film or films over the surface, wherein the film or films retain the serrated profile; depositing a material over the substrate; selectively masking the material to define a masked portion of the material and an unmasked portion of the material; and performing a second etch process to etch a portion of the material and form the material with a sidewall, wherein the second etch process uncovers the serrated profile, and wherein during the second etch process ions are reflected from the serrated profile.
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公开(公告)号：US20250072037A1
公开(公告)日：2025-02-27
申请号：US18407524
申请日：2024-01-09
Inventor： Wei-Lun Min , Chang-Miao Liu , Huiling Shang
IPC: H01L29/78 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/786
Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include bonding a first semiconductor substrate having (110) orientation on a second semiconductor substate having (100) orientation, forming a stack over the first semiconductor substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning the stack to form a fin-shape structure, the fin-shape structure comprising a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench, forming a dielectric film in the source/drain trench, and epitaxially growing an epitaxial feature over the dielectric film, the epitaxial feature being in contact with the plurality of channel layers. The epitaxial feature has (110) orientation.
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公开(公告)号：US20250070094A1
公开(公告)日：2025-02-27
申请号：US18946956
申请日：2024-11-14
Inventor： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong
IPC: H01L25/065 , G11C5/04 , G11C5/06 , H01L23/00 , H01L23/538 , H01L27/06 , H10B61/00
Abstract: A semiconductor package includes a processor die, a storage module and a package substrate. The storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. The package substrate is on which the processor die and the storage module are disposed.
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Patent Agency Ranking
公开(公告)号：US20250070060A1
公开(公告)日：2025-02-27
申请号：US18940884
申请日：2024-11-08
Inventor： JEN-YUAN CHANG , CHIA-PING LAI
IPC: H01L23/00
Abstract: A package structure and method of manufacturing a package structure are provided. The package structure includes two semiconductor structures and two bonding layers sandwiched between both semiconductor structures. Each bonding layer has a plurality of bonding pads separated by an isolation layer. Each bonding pad has a bonding surface including a bonding region and at least one buffer region. The bonding regions in both bonding layers bond to each other. The buffer region of one semiconductor structure bonds to the isolation layer of the other semiconductor structure. Each first bonding pad has a front cross-section with a length greater than a length of a front cross-section of each second bonding pads; and each second bonding pads has a side cross-section with a length greater than a length of a front cross-section of each first bonding pad.
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公开(公告)号：US20250069993A1
公开(公告)日：2025-02-27
申请号：US18942737
申请日：2024-11-10
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC: H01L23/495 , H01L21/48 , H01L21/768 , H01L23/00 , H01L23/498 , H01L23/528 , H01L25/065
Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.
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公开(公告)号：US20250069989A1
公开(公告)日：2025-02-27
申请号：US18238049
申请日：2023-08-25
Inventor： Yen-Chih HUANG , Li-An SUN , Chih-Hao CHEN , Chung-Chuan HUANG
IPC: H01L23/48 , H01L21/768
Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.
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公开(公告)号：US20250069975A1
公开(公告)日：2025-02-27
申请号：US18945476
申请日：2024-11-12
Inventor： Sheng-An Kuo , Ching-Jung Yang , Hsien-Wei Chen , Jie Chen , Ming-Fa Chen
IPC: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/498 , H01L23/538 , H01L25/065
Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
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公开(公告)号：US20250069904A1
公开(公告)日：2025-02-27
申请号：US18943969
申请日：2024-11-12
Inventor： OTTO CHEN , YING-YEN TSENG , WEN-YU KU , CHIA-CHIH CHEN
IPC: H01L21/67
Abstract: A semiconductor fabrication facility is provided. The semiconductor fabrication facility includes a processing tool and a transmission assembly. The transmission assembly is connected to the processing tool and comprises a number of transmission lines used to supply electric power or a fluid to the processing tool or remove the fluid or an exhaust gas from the processing tool. The transmission lines includes a first transmission line and a second transmission line. The first transmission line has a first temperature and the second transmission line has a second temperature. The second temperature is higher than the first temperature. The first transmission line and the second transmission line are arranged such that a thermal energy of the second transmission line is able to be transmitted to the first transmission line to change the first temperature of the first transmission line.
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