公开(公告)号：US09318558B2

公开(公告)日：2016-04-19

申请号：US14413435

申请日：2012-07-09

申请人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

发明人： Toshiyuki Mine ,  Yasuhiro Shimamoto ,  Hirotaka Hamamura

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L29/06 ,  H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/1608 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/12 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7926

摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.

摘要翻译： 本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。 在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域 通道长度方向与具有其它阈值电压的区域相比较。

公开(公告)号：US08617078B2

公开(公告)日：2013-12-31

申请号：US13577816

申请日：2011-01-25

申请人： Shuntaro Machida ,  Taiichi Takezaki ,  Toshiyuki Mine

发明人： Shuntaro Machida ,  Taiichi Takezaki ,  Toshiyuki Mine

IPC分类号： A61B8/00

CPC分类号： B06B1/0292 ,  A61B8/00

摘要： In an ultrasonic transducer comprising a first electrode, a first insulating film disposed on the first electrode, a hollow part provided above the first insulating film and disposed between surfaces above and below the hollow part, a second insulating film disposed above the hollow part, and a second electrode disposed on the second insulating film, a first conductive film disposed on a side of the surface below the hollow part and a second conductive film disposed on a side of the surface above the hollow part are provided, the first conductive film and the second conductive film are disposed so that they overlap with a region in which the surfaces above and below the hollow part contact with each other as seen from above when the transducer is driven, and they do not overlap with each other in the region as seen from above.

摘要翻译： 在包括第一电极的超声换能器中，设置在第一电极上的第一绝缘膜，设置在第一绝缘膜之上并设置在中空部分之上和之下的表面之间的中空部分，设置在中空部分上方的第二绝缘膜，以及 设置在第二绝缘膜上的第二电极，设置在中空部分下方的表面侧的第一导电膜和设置在中空部分上方表面侧的第二导电膜，第一导电膜和 第二导电膜被设置为使得它们与中空部分的上表面和下表面之间的表面彼此重叠的区域与传感器被驱动时从上方观察到，并且它们在区域中彼此不重叠，如从 以上。

公开(公告)号：US08541768B2

公开(公告)日：2013-09-24

申请号：US13118402

申请日：2011-05-28

申请人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

发明人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

IPC分类号： H01L29/02

CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

公开(公告)号：US08427865B2

公开(公告)日：2013-04-23

申请号：US13440225

申请日：2012-04-05

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08410543B2

公开(公告)日：2013-04-02

申请号：US11965391

申请日：2007-12-27

申请人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： H01L27/088

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.

摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的双层结构 沉积有高杂质浓度的多晶硅膜。

公开(公告)号：US20120149143A1

公开(公告)日：2012-06-14

申请号：US13303227

申请日：2011-11-23

申请人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

发明人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

IPC分类号： H01L31/18

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

公开(公告)号：US08106449B2

公开(公告)日：2012-01-31

申请号：US11493688

申请日：2006-07-27

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11 ,  H01L27/11517 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/78

摘要： To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.

摘要翻译： 为了在具有增益单元结构的存储单元中实现稳定的读取操作，构造了写入晶体管，其具有形成在绝缘层上的源极和漏极，形成在绝缘层上并且在源极和 所述漏极由半导体构成，栅极形成在所述绝缘层的上部，所述源极与漏极之间，并且通过栅极绝缘膜与所述沟道电绝缘并控制所述沟道的电位。 通道将源极和漏极的侧表面上的源极和漏极电连接。

公开(公告)号：US20110001179A1

公开(公告)日：2011-01-06

申请号：US12820468

申请日：2010-06-22

申请人： Itaru YANAGI ,  Digh HISAMOTO ,  Daisuke OKADA ,  Atushi YOSHITOMI ,  Yasufumi MORIMOTO ,  Toshiyuki MINE

发明人： Itaru YANAGI ,  Digh HISAMOTO ,  Daisuke OKADA ,  Atushi YOSHITOMI ,  Yasufumi MORIMOTO ,  Toshiyuki MINE

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L29/42344 ,  G11C16/0408 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792

摘要： In a non-volatile memory in which charge is injected from a gate electrode to a charge accumulating layer, charge injection efficiency, charge retention characteristic and reliability are all improved compared with a conventional gate structure. In a nonvolatile memory which carries out write/erasure by changing the total charge amount by injecting electrons and holes into a silicon nitride film which makes up a charge accumulating layer, in order to highly efficiently carry out charge injection from a gate electrode, the gate electrode of a memory cell is made up of a two-layer film of a non-doped polysilicon layer and a metal material electrode layer.

摘要翻译： 在从栅电极向电荷累积层注入电荷的非易失性存储器中，与常规栅极结构相比，电荷注入效率，电荷保持特性和可靠性都得到改善。 在通过将电子和空穴注入构成电荷积聚层的氮化硅膜中来改变总电荷量而进行写入/擦除的非易失性存储器中，为了从栅电极高效地进行电荷注入， 存储单元的电极由非掺杂多晶硅层和金属材料电极层的两层膜构成。

公开(公告)号：US07817811B2

公开(公告)日：2010-10-19

申请号：US11341655

申请日：2006-01-30

申请人： Shinichiro Umemura ,  Takashi Azuma ,  Tatsuya Nagata ,  Hiroshi Fukuda ,  Toshiyuki Mine ,  Syuntaro Machida

发明人： Shinichiro Umemura ,  Takashi Azuma ,  Tatsuya Nagata ,  Hiroshi Fukuda ,  Toshiyuki Mine ,  Syuntaro Machida

IPC分类号： H04R25/00

CPC分类号： B06B1/0292

摘要： The present invention aims to stabilize sound-electricity conversion characteristics of a diaphragm-type sound-electricity conversion device as well as to decrease the noise level of an ultrasonic diagnostic apparatus using the sound-electricity conversion device. The sound-electricity conversion device is configured by a capacitor cell including a lower electrode formed on a silicon substrate and an upper electrode over the lower electrode, the lower and upper electrodes sandwiching a cavity. An electrode short-circuit prevention film is formed on the upper electrode on the cavity side. The electrode short-circuit prevention film is formed of a material with an electrical time constant shorter than 1 second and longer than 10 microseconds, such as silicon nitride containing a stoichiometrically excessive amount of silicon. As a result, the electrode short-circuit prevention film has small electric conductivity, and thus it is made possible to prevent the film from being charged with electric charge and to avoid the drift of the electric charge. Consequently, the sound-electricity conversion characteristics of the sound-electricity conversion device stabilize, and further the sound noise level of the ultrasonic diagnostic apparatus decreases.

摘要翻译： 本发明旨在稳定隔膜式声电转换装置的声电转换特性，并且降低使用声电转换装置的超声波诊断装置的噪声水平。 声电转换装置由包括形成在硅基板上的下电极和下电极上的上电极的电容器单元构成，下电极和上电极夹着空腔。 在空腔侧的上部电极上形成电极短路防止膜。 电极短路防止膜由电气时间常数短于1秒且长于10微秒的材料形成，例如含有化学计量过量的硅的氮化硅。 结果，电极短路防止膜具有小的导电性，因此可以防止膜被充电并避免电荷的漂移。 因此，声电转换装置的声电转换特性稳定，超声波诊断装置的声音噪声水平进一步降低。

公开(公告)号：US07692233B2

公开(公告)日：2010-04-06

申请号：US11446220

申请日：2006-06-05

申请人： Takashi Kobayashi ,  Toshiyuki Mine

发明人： Takashi Kobayashi ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/3145 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825

摘要： A technology capable of improving a charge retention characteristic of a nonvolatile memory is provided. In a memory cell in which an interlayer insulating film formed of an ONO film obtained by laminating a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film is formed between a floating gate formed of a polycrystalline silicon film and a control gate formed of a polycrystalline silicon film, the upper silicon oxide film is formed through LPCVD and is then nitrided through a remote plasma process, thereby introducing nitrogen of, for example, 5 to 6 atom % into the upper surface portion of the upper silicon oxide film.

摘要翻译： 提供了能够提高非易失性存储器的电荷保持特性的技术。 在由多晶硅膜形成的浮动栅极和控制层之间形成由通过层叠下部氧化硅膜，氮化硅膜和上部氧化硅膜而获得的ONO膜形成的层间绝缘膜的存储单元中， 由多晶硅膜形成的栅极，通过LPCVD形成上部氧化硅膜，然后通过远程等离子体工艺进行氮化，从而将例如5至6原子％的氮引入上部氧化硅的上表面部分 电影。