公开(公告)号：US5252851A

公开(公告)日：1993-10-12

申请号：US827254

申请日：1992-01-28

申请人： Keizi Mita ,  Tsuyoshi Takahashi ,  Toshiyuki Ohkoda ,  Tadayoshi Takada

发明人： Keizi Mita ,  Tsuyoshi Takahashi ,  Toshiyuki Ohkoda ,  Tadayoshi Takada

IPC分类号： H01L27/146 ,  H01L27/144 ,  H01L27/14 ,  H01L31/00

CPC分类号： H01L27/1443

摘要： An optical semiconductor is integrated with a transistor by epitaxially growing a lightly doped epitaxial layer on a substrate. One isolated island area of the epitaxial layer contains a diffusion area on its surface to form the optical semiconductor. A second isolated island area has its conductivity type inverted by a buried layer that is diffused upward into contact with a surface layer that is diffused downward. The upward-diffused and downward-diffused layers unite to form a collector of the transistor. A base area in the surface of the collector contains an emitter in its surface. The emitter and the diffusion area are formed of the same material, and in the same process steps.

摘要翻译： 光学半导体通过在衬底上外延生长轻掺杂的外延层而与晶体管集成。 外延层的一个隔离岛区域在其表面上包含扩散区域以形成光学半导体。 第二隔离岛区域的导电类型由埋入层反转，该埋层向上扩散以与向下扩散的表面层接触。 向上扩散和向下扩散的层联合形成晶体管的集电极。 收集器表面的基极区在其表面含有一个发射极。 发射极和扩散区域由相同的材料形成，并且在相同的工艺步骤中。

公开(公告)号：US5141881A

公开(公告)日：1992-08-25

申请号：US510469

申请日：1990-04-18

申请人： Kazuo Takeda ,  Toshimasa Sadakata ,  Teruo Tabata ,  Nobuyuki Sekikawa ,  Tadayoshi Takada ,  Yasuhiro Tamada ,  Yoshiaki Sano

发明人： Kazuo Takeda ,  Toshimasa Sadakata ,  Teruo Tabata ,  Nobuyuki Sekikawa ,  Tadayoshi Takada ,  Yasuhiro Tamada ,  Yoshiaki Sano

IPC分类号： H01L21/761 ,  H01L21/8222

CPC分类号： H01L21/761 ,  H01L21/8222 ,  Y10S148/009 ,  Y10S148/01

摘要： A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

公开(公告)号：US6110772A

公开(公告)日：2000-08-29

申请号：US16512

申请日：1998-01-30

申请人： Tadayoshi Takada ,  Tsuyoshi Takahashi ,  Yasunari Tagami ,  Hirotsugu Hata ,  Satoru Kaneko

发明人： Tadayoshi Takada ,  Tsuyoshi Takahashi ,  Yasunari Tagami ,  Hirotsugu Hata ,  Satoru Kaneko

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/822 ,  H01L27/06 ,  H01L21/70

CPC分类号： H01L27/0635 ,  H01L28/20 ,  H01L28/40

摘要： A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer. The lower and upper electrodes of the capacitor may be formed using an a-Si layer, similar to the resistance layer.

摘要翻译： 一种在电路基板上包括电阻元件的半导体IC。 电阻元件包括形成在绝缘层上的电阻层。 电阻层使用通过形成a-Si层获得的Si层，用杂质掺杂a-Si层并加热掺杂的a-Si层以扩散杂质而形成，同时基本上保持a-Si层的细度 表面。 优选地，设置在电阻层下方的SiN层。 电容器可以集成在形成电阻元件的同一电路基板上。 在这种情况下，依次形成下电极，SiN电介质层和上电极，构成电容器。 电容器的SiN介质层形成为从电容器形成区域延伸到另一区域，使得电阻元件的电阻层形成在延伸的SiN电介质层上。 可以使用类似于电阻层的a-Si层来形成电容器的下电极和上电极。

公开(公告)号：US4898839A

公开(公告)日：1990-02-06

申请号：US271746

申请日：1988-11-15

申请人： Chikao Fujinuma ,  Nobuyuki Sekikawa ,  Teruo Tabata ,  Tadayoshi Takada ,  Yoshiaki Sano ,  Toshimasa Sadakata

发明人： Chikao Fujinuma ,  Nobuyuki Sekikawa ,  Teruo Tabata ,  Tadayoshi Takada ,  Yoshiaki Sano ,  Toshimasa Sadakata

IPC分类号： H01L21/761 ,  H01L21/8248 ,  H01L27/06

CPC分类号： H01L21/761 ,  H01L21/8248 ,  H01L27/0658 ,  Y10S148/014

摘要： A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

摘要翻译： 一种制造半导体集成电路的方法包括以下步骤：形成覆盖半导体衬底和掩埋层的外延层; 形成将外延层分成多个岛的隔离区; 在其中一个岛中形成MIS型电容器的下电极区域; 在另一岛中与下电极同时或独立地形成垂直双极晶体管的基极区; 在所述下电极区域的一部分上沉积所述MIS型电容器的薄介电层; 然后选择性地将杂质扩散到基极区的表面层中，以形成垂直双极晶体管的发射极区; 以及在所述薄介电层上形成所述MIS型电容器的上电极。

公开(公告)号：US5023195A

公开(公告)日：1991-06-11

申请号：US525166

申请日：1990-05-16

申请人： Nobuyuki Sekikawa ,  Tadayoshi Takada

发明人： Nobuyuki Sekikawa ,  Tadayoshi Takada

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

CPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/761 ,  Y10S148/106

摘要： After a base region and a base contact region, a diffused resistance region and a pair of contact regions formed at each end of the diffused resistance region are formed, an silicon oxide film of essentially uniform thickness is formed anew on the surface of an epitaxial layer. In the silicon oxide film, a collector contact/doping window, a base contact window, an emitter contact/doping window, a lower layer electrode contact window, and a diffused resistance element contact window are formed simultaneously, then the base contact region and the diffused resistance element contact regions are shielded by a mask and a collector contact region, an emitter contact region, and a lower layer electrode contact region are doped. The method of manufacturing a semiconductor integrated circuit of the present invention has the advantages that all insulating films have a uniform film thickness, eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions. It is possible to form element regions of the design size and a large margin of spacing for the isolating regions and the base region is unnecessary. A high degree of integration can be achieved.

公开(公告)号：US06545337B2

公开(公告)日：2003-04-08

申请号：US09946216

申请日：2001-09-05

申请人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

发明人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76297 ,  H01L21/8228 ,  H01L27/1203

摘要： Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

摘要翻译： 当形成集电极区域（32,33）时，通过层叠4个外延层，能够承受高电压的膜的集电极区域（32,33）。 为了减少由晶体管（21,22）之间的干扰引起的影响并且还减少了寄生晶体管，外延层和衬底被蚀刻在V沟槽中。 每个蚀刻区域被多晶硅（42）介电隔离。

公开(公告)号：US06528379B2

公开(公告)日：2003-03-04

申请号：US09946948

申请日：2001-09-05

申请人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

发明人： Tadayoshi Takada ,  Osamu Kitamura ,  Shigeaki Okawa ,  Hirotsugu Hata ,  Chikao Fujinuma

IPC分类号： H01L29788

CPC分类号： H01L21/76297 ,  H01L21/76264 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1203

摘要： A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.