公开(公告)号：US20130176797A1

公开(公告)日：2013-07-11

申请号：US13617637

申请日：2012-09-14

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/222

Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

Abstract translation: 数据输出电路包括：控制信号生成块，被配置为生成在第一读取操作中产生的第一传送控制信号和在第二读取操作中产生的第二传送控制信号，其中第一传送控制信号和第二传送控制信号 传入控制信号在进入测试模式时产生; 以及使能信号生成单元，被配置为响应于第一和第二传送控制信号而产生用于产生第一和第二内部时钟的第一和第二使能信号。

公开(公告)号：US20110158032A1

公开(公告)日：2011-06-30

申请号：US12824864

申请日：2010-06-28

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1018 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

Abstract: A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal.

Abstract translation: 提出了一种时钟控制电路，用于减少不必要的电流消耗。 时钟控制电路包括写使能信号生成单元和时钟使能信号生成单元。 写入使能信号生成单元被配置为响应于第一和第二突发信号而生成第一写入使能信号，该第一写入使能信号在写入命令被输入之后的预定时间段期间被使能，并且写入信号包括响应于 写命令。 时钟使能信号生成单元被配置为响应于第一写入信号和第一写入使能信号而生成在写入操作期间使能的时钟使能信号。

公开(公告)号：US20110094251A1

公开(公告)日：2011-04-28

申请号：US12796014

申请日：2010-06-08

Applicant: Kil Young Kim ,  Jin Sung Kim ,  Tae Jin Kang

Inventor： Kil Young Kim ,  Jin Sung Kim ,  Tae Jin Kang

IPC: F25B7/00 ,  F25B1/10

CPC classification number: F25B1/053 ,  F25B1/10 ,  F25B2339/047 ,  F25B2400/0751

Abstract: A dual turbo centrifugal chiller includes: first and second evaporators connected in series or in parallel; first and second condensers connected in series or in parallel; and first and second compressors including impellers, wherein cold water passes through the second evaporator after passing through the first evaporator, and cooling water passes through the second condenser after passing through the first condenser, the first compressor containing a refrigerant connects the first condenser to the second evaporator, and the second compressor containing a refrigerant connects the second condenser to the first evaporator, and the impellers of the first compressor and second compressor are rotated simultaneously using a single driving unit.

Abstract translation: 双涡轮离心式冷冻机包括：串联或并联连接的第一和第二蒸发器; 串联或并联连接的第一和第二电容器; 以及包括叶轮的第一和第二压缩机，其中冷水在通过第一蒸发器之后通过第二蒸发器，并且冷却水在通过第一冷凝器之后通过第二冷凝器，含有制冷剂的第一压缩机将第一冷凝器连接到 第二蒸发器，并且包含制冷剂的第二压缩机将第二冷凝器连接到第一蒸发器，并且使用单个驱动单元同时旋转第一压缩机和第二压缩机的叶轮。

公开(公告)号：US20090237139A1

公开(公告)日：2009-09-24

申请号：US12215774

申请日：2008-06-30

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03L5/00

CPC classification number: H03K3/35613 ,  H03K3/012

Abstract: A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode.

Abstract translation: 电平移位器包括电平移位单元，用于将处于第一电压电平的输入信号电平转换为第二电压电平的信号;以及输出控制器，用于控制电平移位单元，以响应于电平移位单元将输出维持在预定逻辑电平 在深度掉电模式下从未关闭的电源产生的深度掉电模式信号。

公开(公告)号：US20090074207A1

公开(公告)日：2009-03-19

申请号：US12283774

申请日：2008-09-16

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: H03G5/00 ,  H04M1/00

CPC classification number: H04R3/04 ,  H03G5/025 ,  H04M1/6016 ,  H04M1/72572

Abstract: A mobile communication device and a method of setting tone color, which allow a user to set the tone color of received sound. Provided are a normal mode, which sets the equalizer using GCF standards stored in an internal memory or equalizer setting values selected by a provider, a country-specific mode, which uses country-specific setting, and a user mode, in which a user can set frequency-specific gains of the received sound, and one mode is selected from the provided mode, so that the tone color of the received sound can be adjusted according to the selection. Telephone speech quality can be optimized for user preference, network environments and language characteristics.

Abstract translation: 移动通信设备和设置音色的方法，其允许用户设置接收到的声音的色调。 提供了一种正常模式，其使用存储在内部存储器中的GCF标准或由提供商选择的均衡器设置值，使用国家特定设置的国家/地区模式以及用户可以使用的用户模式来设置均衡器 设置接收到的声音的特定频率增益，并且从提供的模式中选择一种模式，使得可以根据选择来调整接收到的声音的音色。 电话语音质量可以针对用户偏好，网络环境和语言特性进行优化。

公开(公告)号：US07366050B2

公开(公告)日：2008-04-29

申请号：US11178561

申请日：2005-07-12

Applicant: Tae-Jin Kang ,  Bong-Hwa Jeong

Inventor： Tae-Jin Kang ,  Bong-Hwa Jeong

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

公开(公告)号：US20050094853A1

公开(公告)日：2005-05-05

申请号：US10758868

申请日：2004-01-16

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: G01B11/24 ,  G01N21/88 ,  G01N21/89 ,  G01N21/898 ,  G06K9/00 ,  G06T7/00

CPC classification number: G06T7/0004 ,  G01N21/8851 ,  G01N21/8901 ,  G01N21/8983 ,  G01N2021/1772 ,  G01N2021/1785 ,  G01N2021/8861 ,  G01N2021/8896 ,  G01N2021/8908 ,  G06T2207/30124

Abstract: The present invention relates to a objective measurement of fabric pillings, to a measurement apparatus which includes stereovision technique using CCD cameras, captures the 3-dimensional contours of fabric pilling and defines the degree of pilling occurrences. This invention is composed of; a step to scan the surface of a pilling-containing fabric specimen which is laid on the table and translated in the right angle of the projector laser beam; a step to reconstruct the scanned fabric surface data in to a 3D image; a step to convert the 3D image into a binary image using height-threshold method and number, area, density of pillings acquired from standard pictures; a step to calculate the x, y coordinates and height values of each and every area of the specimen; a step to regress the relationship between the height values of the pilling fabric specimen and the actual height values. Thus the measurement of fabric surface pillings using stereovision method which is composed of slit beam laser projector and a couple of CCD cameras can be a fast and accurate evaluation method regardless of the fabric's color and pattern shape.

Abstract translation: 本发明涉及一种对织物支柱的客观测量，包括使用CCD照相机的立体视觉技术的测量装置，捕捉织物起球的三维轮廓并定义起球发生的程度。 本发明由 扫描放置在桌子上并且以投影仪激光束的直角平移的起球含织物样品的表面的步骤; 将扫描的织物表面数据重建成3D图像的步骤; 使用高度阈值法和从标准图像获取的数量，面积，密度的密度将3D图像转换为二进制图像的步骤; 计算样本每个区域的x，y坐标和高度值的步骤; 退化起毛织物样品的高度值与实际高度值之间的关系的步骤。 因此，无论织物的颜色和图案形状如何，使用由狭缝光束激光投影仪和两个CCD照相机组成的使用立体视觉方法的织物表面丸的测量可以是快速和准确的评估方法。

公开(公告)号：US09123991B2

公开(公告)日：2015-09-01

申请号：US13035099

申请日：2011-02-25

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: H04R1/10 ,  H01Q1/27 ,  H01Q1/24 ,  H01Q1/46 ,  H01Q1/50 ,  H04M1/60 ,  H04M1/725

CPC classification number: H01Q1/273 ,  H01Q1/241 ,  H01Q1/46 ,  H01Q1/50 ,  H04M1/6058 ,  H04M1/72522

Abstract: An ear-microphone for connection to a portable apparatus and use as a Frequency Modulation (FM) radio broadcast receiving antenna is provided. The ear-microphone includes an ear plug, a cable, a microphone, and a filtering unit. The ear plug is for connection to an earjack. The cable has a predefined length, has an earphone line whose one end is electrically connected to the ear plug and whose other end is electrically connected to at least one earphone. The microphone intervenes in an intermediate portion of the cable and is connected to the ear plug via a microphone line inside the cable. The filtering unit intervenes in the cable and is installed to have an Electro Static Discharge (ESD) protection function.

Abstract translation: 提供一种用于连接到便携式设备并用作频率调制（FM）无线电广播接收天线的耳麦克风。 耳麦麦克风包括耳塞，电缆，麦克风和过滤单元。 耳塞用于连接耳塞。 电缆具有预定长度，具有耳机线，其一端电连接到耳塞，另一端电连接至至少一个耳机。 麦克风插入电缆的中间部分，并通过电缆内的麦克风线连接到耳塞。 过滤单元插入电缆中，并安装有静电放电（ESD）保护功能。

公开(公告)号：US09058859B2

公开(公告)日：2015-06-16

申请号：US13617637

申请日：2012-09-14

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/222

Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

Abstract translation: 数据输出电路包括：控制信号生成块，被配置为生成在第一读取操作中产生的第一传送控制信号和在第二读取操作中产生的第二传送控制信号，其中第一传送控制信号和第二传送控制信号 传入控制信号在进入测试模式时产生; 以及使能信号生成单元，被配置为响应于第一和第二传送控制信号而产生用于产生第一和第二内部时钟的第一和第二使能信号。

公开(公告)号：US08867302B2

公开(公告)日：2014-10-21

申请号：US13096669

申请日：2011-04-28

Applicant: Kyoung Hwan Kwon ,  Tae Jin Kang ,  Sang Kwon Lee

Inventor： Kyoung Hwan Kwon ,  Tae Jin Kang ,  Sang Kwon Lee

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract translation: 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。