公开(公告)号：USD731382S1

公开(公告)日：2015-06-09

申请号：US29473154

申请日：2013-11-19

Applicant: Dinesh Mana ,  Taehoon Kim

Designer： Dinesh Mana ,  Taehoon Kim

公开(公告)号：US08970046B2

公开(公告)日：2015-03-03

申请号：US13546163

申请日：2012-07-11

Applicant: Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

Inventor： Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract translation: 半导体封装可以包括：衬底，其包括衬底连接端子，堆叠在衬底上并具有芯片连接端子的至少一个半导体芯片，覆盖衬底和至少一个半导体芯片的至少一部分的第一绝缘层和/ 或穿透第一绝缘层的互连以将衬底连接端子连接到芯片连接端子。 半导体封装可以包括堆叠的半导体芯片，半导体芯片的边缘部分构成阶梯结构，并且每个半导体芯片包括芯片连接端子; 至少一个绝缘层，至少覆盖半导体芯片的边缘部分; 和/或穿透至少一个绝缘层的互连以连接到每个半导体芯片的芯片连接端子。

公开(公告)号：US08717823B2

公开(公告)日：2014-05-06

申请号：US13537150

申请日：2012-06-29

Applicant: Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

Inventor： Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

Abstract translation: 一系列编程脉冲被施加到要编程的存储器单元。 在每个编程脉冲之后，在初始程序验证电压下将程序验证脉冲施加到存储单元。 初始程序验证电压是通过快速充电损耗电压增加的验证电压。 在编程脉冲达到某个参考电压或编程脉冲数达到脉冲计数阈值之后，从初始编程验证电压中减去快速充电损耗电压。

公开(公告)号：US20120140567A1

公开(公告)日：2012-06-07

申请号：US13366557

申请日：2012-02-06

Applicant: Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

Inventor： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

Abstract translation: 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US20120098446A1

公开(公告)日：2012-04-26

申请号：US13340238

申请日：2011-12-29

Applicant: Taehoon KIM ,  Junwan Bang ,  Heegu Park

Inventor： Taehoon KIM ,  Junwan Bang ,  Heegu Park

IPC: H05B37/02

CPC classification number: H05B37/0272

Abstract: A lighting system automatically assigns a unique address to each lighting apparatus, and controls each lighting apparatus based on the assigned address. The lighting system may include a first lighting apparatus, a second lighting apparatus connected to the first lighting apparatus in series, and a bridge device coupled to the first and second lighting apparatuses in series and configured to assign an address to the first and second lighting apparatuses. The bridge device may transmit a first data packet to initialize the lighting apparatuses for address assignment, and a control circuit may disconnect the connections between the lighting apparatuses during address assignment.

Abstract translation: 照明系统为每个照明装置自动分配唯一的地址，并且基于所分配的地址控制每个照明装置。 照明系统可以包括串联连接到第一照明装置的第一照明装置，第二照明装置和串联连接到第一和第二照明装置的桥式装置，并且被配置为向第一和第二照明装置分配地址 。 桥接设备可以发送第一数据分组以初始化用于地址分配的照明设备，并且控制电路可以在地址分配期间断开照明设备之间的连接。

公开(公告)号：US08111555B2

公开(公告)日：2012-02-07

申请号：US12696279

申请日：2010-01-29

Applicant: Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

Inventor： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

Abstract translation: 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US07794820B2

公开(公告)日：2010-09-14

申请号：US11878165

申请日：2007-07-20

Applicant: Dong Sun Kim ,  Taehoon Kim ,  Jong Seok Song ,  Sam Jin Her ,  Jun Heyoung Park

Inventor： Dong Sun Kim ,  Taehoon Kim ,  Jong Seok Song ,  Sam Jin Her ,  Jun Heyoung Park

IPC: B32B15/00

CPC classification number: H05K3/381 ,  H05K1/0346 ,  H05K3/108 ,  H05K3/146 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/092 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.

Abstract translation: 这里公开了一种印刷电路板及其制造方法，其可以通过实现超薄精细电路图案来改善电性能，缩短处理时间并减小芯片封装的厚度。 印刷电路板包括绝缘材料; 形成在绝缘材料的给定位置的通孔; 通过离子束表面处理形成的铜籽晶层，并且在其中形成有通孔的绝缘材料的表面上真空沉积; 以及形成在其上形成有铜种子层的绝缘材料的给定区域上的铜图案镀层和通孔。

公开(公告)号：US20080273385A1

公开(公告)日：2008-11-06

申请号：US11800002

申请日：2007-05-03

Applicant: Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

Inventor： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

Abstract translation: 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US20070261234A1

公开(公告)日：2007-11-15

申请号：US11709215

申请日：2007-02-22

Applicant: Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

Inventor： Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

IPC: H01K3/10 ,  H05K3/10 ,  H05K3/02

CPC classification number: H05K3/381 ,  H05K3/108 ,  H05K3/146 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2203/092 ,  H05K2203/1152 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.

Abstract translation: 公开了一种积层印刷电路板的制造方法，其中通过使用干法形成芯层的金属种子层来实现包括芯层和外层的积层印刷电路板的电路 ，由离子束表面处理和真空沉积组成，代替常规的湿法，包括湿表面粗糙化处理和无电镀。 当在本发明的方法中用干法代替湿法时，电路层可以以环境友好的方式形成，并且可以制造包括芯层和外层的基片的所有电路层 通过半加成过程。 此外，可以提高树脂基板和金属层之间的剥离强度，从而实现高可靠性的精细电路。

公开(公告)号：US20120326310A1

公开(公告)日：2012-12-27

申请号：US13499809

申请日：2010-10-01

Applicant: Ahmed Busnaina ,  Cihan Yilmaz ,  TaeHoon Kim ,  Sivasubramanian Somu

Inventor： Ahmed Busnaina ,  Cihan Yilmaz ,  TaeHoon Kim ,  Sivasubramanian Somu

IPC: C25B15/00 ,  C25B11/02 ,  H01L23/482 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: H01L21/76879 ,  B82Y10/00 ,  B82Y30/00 ,  C25D13/00 ,  H01L21/2885 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanaotubes.

Abstract translation: 本发明提供了用于从纳米颗粒制造金属纳米棒的快速，可扩展的室温工艺，或者从悬浮在水溶液中的碳纳米管制造金属或半导体纳米棒。 组装的纳米棒适合用作基于CMOS的器件和传感器中的纳米级互连。 通过施加外部电场将金属纳米颗粒或碳纳米管组装成光刻图案化的通孔。 由于纳米棒的尺寸由通孔的尺寸控制，纳米棒尺寸可以缩小到低纳米范围。 水性组合方法是环境友好的，并且可以用于制备使用不同类型的金属颗粒以及半导体和金属纳米管的纳米棒。