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    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20110216616A1

    公开(公告)日：2011-09-08

    申请号：US13014522

    申请日：2011-01-26

    申请人： Tai-Young Ko

    发明人： Tai-Young Ko

    IPC分类号： G11C7/06

    CPC分类号： G11C7/06

    摘要： A semiconductor memory device includes a first and second memory cell array region, a first and second sense amplifier region interposed between the first and second memory cell array regions, a first column selection region interposed between the first sense amplifier region and the first memory cell array region and including a first column selection transistor connected between a first bit line and a first local data input/output (I/O) line, and a second column selection region interposed between the second sense amplifier region and the second memory cell array region and including a second column selection transistor connected between a second bit line and a second local data I/O line. A load of the second bit line is larger than a load of the first bit line and a threshold voltage of the first column selection transistor is higher than a threshold voltage of the second column selection transistor.

    摘要翻译： 半导体存储器件包括第一和第二存储单元阵列区域，插入在第一和第二存储单元阵列区域之间的第一和第二读出放大器区域，插入在第一读出放大器区域和第一存储单元阵列之间的第一列选择区域 并且包括连接在第一位线和第一本地数据输入/输出（I / O）线之间的第一列选择晶体管，以及插入在第二读出放大器区域和第二存储单元阵列区域之间的第二列选择区域，以及 包括连接在第二位线和第二本地数据I / O线之间的第二列选择晶体管。 第二位线的负载大于第一位线的负载，第一列选择晶体管的阈值电压高于第二列选择晶体管的阈值电压。

    Semiconductor memory device for reducing bit line coupling noise
    4.
    发明授权
    Semiconductor memory device for reducing bit line coupling noise 有权
    用于减少位线耦合噪声的半导体存储器件

    公开(公告)号：US08467216B2

    公开(公告)日：2013-06-18

    申请号：US12917832

    申请日：2010-11-02

    申请人： Sang-yun Kim ,  Tai-young Ko

    发明人： Sang-yun Kim ,  Tai-young Ko

    IPC分类号： G11C5/06

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

    摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

    摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

    Methods and devices for regulating the timing of control signals in integrated circuit memory devices
    5.
    发明授权
    Methods and devices for regulating the timing of control signals in integrated circuit memory devices 有权
    用于调节集成电路存储器件中控制信号时序的方法和装置

    公开(公告)号：US07688651B2

    公开(公告)日：2010-03-30

    申请号：US11756750

    申请日：2007-06-01

    申请人： Chi-wook Kim ,  Tai-young Ko

    发明人： Chi-wook Kim ,  Tai-young Ko

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

    摘要： A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

    摘要翻译： 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。

    SIGNAL AMPLIFICATION CIRCUIT FOR HIGH-SPEED OPERATION AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    6.
    发明申请
    SIGNAL AMPLIFICATION CIRCUIT FOR HIGH-SPEED OPERATION AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 审中-公开
    用于高速操作的信号放大电路和具有该功能的半导体存储器件

    公开(公告)号：US20060250162A1

    公开(公告)日：2006-11-09

    申请号：US11379200

    申请日：2006-04-18

    申请人： Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

    发明人： Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

    IPC分类号： H03F3/45

    CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1069

    摘要： A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.

    摘要翻译： 一种用于半导体存储器件的信号放大电路包括：电流检测放大器，被配置为接收第一信号对并在第一对线路上产生第二信号对，配置成对第一对线路进行均衡的均衡器和配置成 以响应于第二信号对在第二对线路上产生锁存数据输出。

    SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE 有权
    用于减少位线耦合噪声的半导体存储器件

    公开(公告)号：US20110182099A1

    公开(公告)日：2011-07-28

    申请号：US12917832

    申请日：2010-11-02

    申请人： Sang-yun Kim ,  Tai-young Ko

    发明人： Sang-yun Kim ,  Tai-young Ko

    IPC分类号： G11C5/02

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

    摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

    摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

    WORDLINE DRIVING CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY
    8.
    发明申请
    WORDLINE DRIVING CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY 有权
    WORDLINE驱动电路和半导体存储器的方法

    公开(公告)号：US20080080296A1

    公开(公告)日：2008-04-03

    申请号：US11835766

    申请日：2007-08-08

    申请人： Hong-Jun Lee ,  Tai-Young Ko

    发明人： Hong-Jun Lee ,  Tai-Young Ko

    IPC分类号： G11C8/08 ,  G11C8/10

    CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2207/2227

    摘要： Provided is a wordline driving circuit and method for a semiconductor memory, in which the wordline driving circuit includes an address decoding signal generator and a wordline voltage supplier. The address decoding signal generator receives a first row address decoding signal (URA) and generates a delayed URA signal (PXID). The wordline voltage supplier has a pull-up transistor for providing the PXID signal to a selected wordline in response to a second row address decoding signal (LRA). The address decoding signal generator sets the PXID signal to a floating state before the selection of the wordline to prevent a leakage current from flowing through the pull-up transistor in a standby mode.

    摘要翻译： 提供一种用于半导体存储器的字线驱动电路和方法，其中字线驱动电路包括地址解码信号发生器和字线电压供应器。 地址解码信号发生器接收第一行地址解码信号（URA）并产生延迟的URA信号（PXID）。 字线电压供应器具有上拉晶体管，用于响应于第二行地址解码信号（LRA）将PXID信号提供给选定的字线。 地址解码信号发生器在选择字线之前将PXID信号设置为浮置状态，以防止在备用模式下漏电流流过上拉晶体管。

    METHODS AND DEVICES FOR REGULATING THE TIMING OF CONTROL SIGNALS IN INTEGRATED CIRCUIT MEMORY DEVICES
    9.
    发明申请
    METHODS AND DEVICES FOR REGULATING THE TIMING OF CONTROL SIGNALS IN INTEGRATED CIRCUIT MEMORY DEVICES 有权
    用于调整集成电路存储器件中控制信号时序的方法和装置

    公开(公告)号：US20070280033A1

    公开(公告)日：2007-12-06

    申请号：US11756750

    申请日：2007-06-01

    申请人： Chi-wook Kim ,  Tai-young Ko

    发明人： Chi-wook Kim ,  Tai-young Ko

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00 ,  G11C7/02

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

    摘要： A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

    摘要翻译： 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。

    SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR REDUCING BIT LINE COUPLING NOISE 审中-公开
    用于减少位线耦合噪声的半导体存储器件

    公开(公告)号：US20130250645A1

    公开(公告)日：2013-09-26

    申请号：US13897515

    申请日：2013-05-20

    申请人： Sang-yun Kim ,  Tai-young Ko

    发明人： Sang-yun Kim ,  Tai-young Ko

    IPC分类号： G11C5/06

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

    摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

    摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。