公开(公告)号：US08841976B2

公开(公告)日：2014-09-23

申请号：US13345974

申请日：2012-01-09

申请人： Taiji Ogawa ,  Hirohito Watanabe ,  Masazaku Sato

发明人： Taiji Ogawa ,  Hirohito Watanabe ,  Masazaku Sato

IPC分类号： H01P3/08 ,  H05K1/02

CPC分类号： H05K1/024 ,  H01P3/081 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681

摘要： The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.

摘要翻译： 印刷电路板具有由第二绝缘层20覆盖的第一绝缘层10的一面上的信号线41的导体和两条导线42，同时在其相对面上具有接地层30的电位的地层， 第二绝缘层（绝缘层A）20的介质切线A大于第一绝缘层（绝缘层B）10的介质切线B，关系式1（相对介电常数B）·（宽（W41） 信号线41）/（第一绝缘层（绝缘层B）的厚度（T10））10）>（相对介电常数A）·{（信号线的厚度（T41）41）/（距离（S1 信号线41和一根导线42a之间）+（信号线41的厚度（T41））/（信号线41与其他导线42b的距离（S2））+（厚度 信号线41的（T41）/（信号线对（41a，41b）·2之间的距离（S3））满足。

公开(公告)号：US20120175158A1

公开(公告)日：2012-07-12

申请号：US13427328

申请日：2012-03-22

申请人： Taiji OGAWA

发明人： Taiji OGAWA

IPC分类号： H05K1/09 ,  H05K1/00

CPC分类号： H05K1/111 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/10734 ,  Y02P70/611

摘要： A circuit board 1 comprises: an insulating substrate 10; and electric circuit patterns 20 formed on the insulating substrate 10. Each electric circuit pattern 20 has: a mounting pad section 30; and a wiring section 40 extending from the mounting pad section 30. The mounting pad section 30 has a first nonparallel surface 32a inclined to or substantially orthogonally intersecting a main surface 41 of the wiring section 40.

摘要翻译： 电路板1包括：绝缘基板10; 和形成在绝缘基板10上的电路图案20.每个电路图案20具有：安装焊盘部分30; 以及从安装焊盘部分30延伸的布线部分40.安装焊盘部分30具有与布线部分40的主表面41倾斜或基本上垂直相交的第一非平行表面32a。

公开(公告)号：US20120279050A1

公开(公告)日：2012-11-08

申请号：US13462399

申请日：2012-05-02

申请人： Hirohito WATANABE ,  Taiji OGAWA ,  Takaomi Tomonaga ,  Eriko TOMONAGA

发明人： Hirohito WATANABE ,  Taiji OGAWA ,  Takaomi Tomonaga ,  Eriko TOMONAGA

IPC分类号： H05K3/00

CPC分类号： H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

摘要： Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

摘要翻译： 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。

公开(公告)号：US20120205141A1

公开(公告)日：2012-08-16

申请号：US13345974

申请日：2012-01-09

申请人： Taiji OGAWA ,  Hirohito WATANABE ,  Masakazu SATO

发明人： Taiji OGAWA ,  Hirohito WATANABE ,  Masakazu SATO

IPC分类号： H05K1/02

CPC分类号： H05K1/024 ,  H01P3/081 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681

摘要： The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.

摘要翻译： 印刷电路板具有由第二绝缘层20覆盖的第一绝缘层10的一面上的信号线41的导体和两条导线42，同时在其相对面上具有接地层30的电位的地层， 第二绝缘层（绝缘层A）20的介质切线A大于第一绝缘层（绝缘层B）10的介质切线B，关系式1（相对介电常数B）·（宽（W41） 信号线41）/（第一绝缘层（绝缘层B）的厚度（T10））10）>（相对介电常数A）·{（信号线的厚度（T41）41）/（距离（S1 信号线41和一根导线42a之间）+（信号线41的厚度（T41））/（信号线41与其他导线42b的距离（S2））+（厚度 信号线41的（T41）/（信号线对（41a，41b）·2之间的距离（S3））满足。

公开(公告)号：US08574449B2

公开(公告)日：2013-11-05

申请号：US13462399

申请日：2012-05-02

申请人： Hirohito Watanabe ,  Taiji Ogawa ,  Eriko Tomonaga

发明人： Hirohito Watanabe ,  Taiji Ogawa ,  Takaomi Tomonaga

IPC分类号： B44C1/22

CPC分类号： H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

摘要： Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

摘要翻译： 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并且对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。