公开(公告)号：US08930869B2

公开(公告)日：2015-01-06

申请号：US13075632

申请日：2011-03-30

申请人： Ikuo Ohtsuka ,  Eiichi Konno ,  Takahiko Orita ,  Yoshitaka Nishio ,  Toshiyasu Sakata

发明人： Ikuo Ohtsuka ,  Eiichi Konno ,  Takahiko Orita ,  Yoshitaka Nishio ,  Toshiyasu Sakata

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.

摘要翻译： 一种用于使计算机执行总线的产生路径的布线设计辅助方法，使得总线相对于包括至少一个布线层的布线区域彼此不相交，所述路径由相应的图形表示。 计算机还对每个总线进一步验证是否从总线连接的部件成功提取属于总线的网线; 并且在布线区域中记录表示属于总线的网络的图形，在该验证中确定属于总线的所有网络被成功提取。 相对于在验证中确定的总线，重新执行总线路径生成至少一个网络未成功提取。

公开(公告)号：US20130132921A1

公开(公告)日：2013-05-23

申请号：US13591844

申请日：2012-08-22

申请人： Takahiko ORITA

发明人： Takahiko ORITA

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.

摘要翻译： 计算机可读记录介质存储使计算机执行电路设计过程的程序。 该过程包括从包括第一连接器组件数据的第一板数据和包括与第一连接器组件数据相关联的第二连接器组件数据的第二板数据中选择第一板数据中的组件数据; 将所选择的组件数据的连接目的地网络名称设置到所述第一连接器组件数据的第一空闲终端; 以及当所述组件数据从所述第一板数据移动到所述第二板数据时，将所述组件数据的连接目的地网络名称设置为与所述第一连接器数据的所述第一空闲终端对应的所述第二连接器组件数据的第二空闲终端 。

公开(公告)号：US08443333B2

公开(公告)日：2013-05-14

申请号：US13044166

申请日：2011-03-09

申请人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

发明人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

IPC分类号： G06F15/04 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.

摘要翻译： 存储设计支持程序的非暂时计算机可读记录介质使计算机执行：获取多条布线路径的不符合线路长度; 基于布线路径的线路长度和布线路径，对每个布线路径绘制连接发送原点和发送目的地的布线图案; 并且控制绘图以为每个布线路径绘制一条线，将被划分为在采集时获取的不合格线长度的第一条线和第二条线的线作为不符合线路长度的布线通路 。

公开(公告)号：US08402413B2

公开(公告)日：2013-03-19

申请号：US12721716

申请日：2010-03-11

申请人： Ikuo Ohtsuka ,  Takao Yamaguchi ,  Eiichi Konno ,  Toshiyasu Sakata ,  Takahiko Orita

发明人： Ikuo Ohtsuka ,  Takao Yamaguchi ,  Eiichi Konno ,  Toshiyasu Sakata ,  Takahiko Orita

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  G06F17/5077 ,  H05K2201/10734

摘要： A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

摘要翻译： 一种用于设计包括以矩阵形式布置的多个连接柱的印刷电路板的多条布线的布线设计装置，包括处理器，所述处理器提供正交网格，所述正交网格包括在所述连接之间和之间运行的多个行和列 柱，其提供多个对角线路径，每个对角线路径至少连接一条行，每条列中的至少一列在相邻的每对连接柱之间运行，并且通过专门地分配给每个布线来确定每个布线的路线 的布线选定部分的列，列和路径，使得所选择的部分连接每条布线的两端。

公开(公告)号：US20090125861A1

公开(公告)日：2009-05-14

申请号：US12222229

申请日：2008-08-05

申请人： Takahiko Orita ,  Eiichi Konno

发明人： Takahiko Orita ,  Eiichi Konno

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards.

摘要翻译： 布线设计处理方法是通过使用计算机将印刷电路板的自动布线处理中的各种处理的执行顺序设计为自动布线处理处理。 布线设计处理方法包括：在各个印刷电路板中，在存储单元中存储包括关于印刷电路板的各种物理信息的印刷电路板信息; 根据针对每个印刷电路板分析设置，布线进展和布线情况的结果，在针对每个印刷电路板读取存储在存储单元中的印刷电路板信息之后，自动创建自动布线处理过程 的印刷电路板; 并且对于每个印刷电路板，根据在创建时创建的自动布线处理过程执行自动布线处理。

公开(公告)号：US20120206460A1

公开(公告)日：2012-08-16

申请号：US13355828

申请日：2012-01-23

申请人： Tomo Kaniwa ,  Takahiko Orita

发明人： Tomo Kaniwa ,  Takahiko Orita

IPC分类号： G06T11/20

CPC分类号： G06T11/203

摘要： A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.

摘要翻译： 一种设备包括处理器，该处理器包括生成通过将第一图形的第一边的每一个朝向第一图形的内部的方向移动长度而识别的第二图形的数据，并且沿着第一图形的方向 在移动之后的第一边之间的移动和交点之后的两边之间，通过将第二图形的第二边的每一侧移动到第二边的每一边的长度，并且通过将第二图形的端点 在移动之后的第二侧使用在移动之前以第二侧的终点为中心并且具有长度的半径的圆弧，并且通过在第二图形和第二图形之间执行逻辑加法运算来生成第四图形的数据 第三个图形。

公开(公告)号：US07984413B2

公开(公告)日：2011-07-19

申请号：US12222229

申请日：2008-08-05

申请人： Takahiko Orita ,  Eiichi Konno

发明人： Takahiko Orita ,  Eiichi Konno

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards.

摘要翻译： 布线设计处理方法是通过使用计算机将印刷电路板的自动布线处理中的各种处理的执行顺序设计为自动布线处理处理。 布线设计处理方法包括：在各个印刷电路板中，在存储单元中存储包括关于印刷电路板的各种物理信息的印刷电路板信息; 根据针对每个印刷电路板分析设置，布线进展和布线情况的结果，在针对每个印刷电路板读取存储在存储单元中的印刷电路板信息之后，自动创建自动布线处理过程 的印刷电路板; 并且对于每个印刷电路板，根据在创建时创建的自动布线处理过程执行自动布线处理。

公开(公告)号：US08847971B2

公开(公告)日：2014-09-30

申请号：US13355828

申请日：2012-01-23

申请人： Tomo Kaniwa ,  Takahiko Orita

发明人： Tomo Kaniwa ,  Takahiko Orita

IPC分类号： G06T11/20 ,  G09G5/37 ,  G06F17/50

CPC分类号： G06T11/203

摘要： A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.

摘要翻译： 一种设备包括处理器，该处理器包括生成通过将第一图形的第一边的每一个朝向第一图形的内部的方向移动长度而识别的第二图形的数据，并且沿着第一图形的方向 在移动之后的第一边之间的移动和交点之后的两边之间，通过将第二图形的第二边的每一侧移动到第二边的每一边的长度，并且通过将第二图形的端点 在移动之后的第二侧使用在移动之前以第二侧的终点为中心并且具有长度的半径的圆弧，并且通过在第二图形和第二图形之间执行逻辑加法运算来生成第四图形的数据 第三个图形。

公开(公告)号：US08402422B2

公开(公告)日：2013-03-19

申请号：US13048687

申请日：2011-03-15

申请人： Toshiyasu Sakata ,  Eiichi Konno ,  Takahiko Orita ,  Kazunori Kumagai

发明人： Toshiyasu Sakata ,  Eiichi Konno ,  Takahiko Orita ,  Kazunori Kumagai

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.

摘要翻译： 一种布线设计装置，用于在包括多个导电层的印刷线路板上进行布线设计，所述布线设计装置包括：噪声污染部分提取装置，用于在噪声污染信号的情况下提取部分，所述部分在 基于线路的路线和路线周围的物理条件进行布线设计的线路; 路线修改处理装置，用于通过在噪声污染信号的情况下将提取的部分移动到行上来修改行的路线到避免噪声污染信号的状况的位置; 以及线长调整装置，用于当线路的线路长度的变化由于改变线路的路线而发生时，进行线路上的线路长度调整以补偿线路的线路长度的变化。

公开(公告)号：US08307322B2

公开(公告)日：2012-11-06

申请号：US12574071

申请日：2009-10-06

申请人： Eiichi Konno ,  Yoshitaka Nishio ,  Takao Yamaguchi ,  Toshiyasu Sakata ,  Takahiko Orita

发明人： Eiichi Konno ,  Yoshitaka Nishio ,  Takao Yamaguchi ,  Toshiyasu Sakata ,  Takahiko Orita

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design apparatus includes a first acquirer that acquires a first wiring block whose region has a maximum number of crossings with regions of other wiring blocks from printed circuit board data of a printed circuit board having a plurality of wiring blocks with a specific region on a wiring layer, a second acquirer that acquires second wiring blocks whose region does not cross the first wiring block from the printed circuit board data, and a wiring execution requester that causes a wiring processor to perform wiring processing on the first wiring block and the second wiring blocks in parallel.

摘要翻译： 布线设计装置包括：第一获取器，其获取与具有特定区域的多个布线块的印刷电路板的印刷电路板数据的区域具有与其他布线块的区域最大交叉数的第一布线块， 布线层，从印刷电路板数据获取区域不与第一布线块相交的第二布线块的第二获取器以及使布线处理器对第一布线块和第二布线进行布线处理的布线执行请求器 块并行