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公开(公告)号：US08467231B2
公开(公告)日：2013-06-18
申请号：US13193756
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C16/02
摘要： The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.
摘要翻译： 使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。 当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以长时间保存数据。 此外，信号线中的电位变化的定时相对于写入字线的电位变化的定时被延迟。 这使得可以防止数据写入错误。
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公开(公告)号：US08357963B2
公开(公告)日：2013-01-22
申请号：US13185965
申请日：2011-07-19
申请人： Kiyoshi Kato , Takanori Matsuzaki
发明人： Kiyoshi Kato , Takanori Matsuzaki
IPC分类号： H01L27/108
CPC分类号： H01L27/11521 , H01L27/108 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1225
摘要： A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j−1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.
摘要翻译： 半导体器件包括晶体管的截止电流足够小的材料; 例如，使用氧化物半导体材料。 此外，包括氧化物半导体材料的半导体器件的存储单元的晶体管串联连接。 此外，使用相同的布线（第j字线（j为大于等于2且小于等于m的自然数））作为与j的电容器的端子之一电连接的布线 第（j-1）个存储单元和与第一第（j-1）个存储单元形成沟道的晶体管的栅极端子电连接的布线。 因此，每个存储单元的布线数和一个存储单元占用的面积减少。
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公开(公告)号：US20120286268A1
公开(公告)日：2012-11-15
申请号：US13558694
申请日：2012-07-26
IPC分类号： H01L27/07
CPC分类号： H03D1/18 , H01L27/1225
摘要： An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.
摘要翻译： 目的在于提供具有足够的解调能力的解调电路。 另一个目的是提供使用具有足够的解调能力的解调电路的RFID标签。 在解调电路中包括的晶体管的一部分中使用能使反向电流足够小的材料，例如，宽带隙半导体的氧化物半导体材料。 通过使用能够使晶体管的反向电流足够小的半导体材料，即使接收到具有高振幅的电磁波也能够确保足够的解调能力。
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公开(公告)号：US20120236621A1
公开(公告)日：2012-09-20
申请号：US13489628
申请日：2012-06-06
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： G11C5/06
CPC分类号： H01L27/108 , G11C11/4023 , H01L27/10894
摘要： A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is electrically connected to a bit line. One terminal of the capacitor is electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor is electrically connected to a wiring. One terminal of one of the resistor and the diode is electrically connected to the other of the source and the drain of the transistor, and the other terminal of one of the resistor and the diode is electrically connected to the wiring.
摘要翻译： 提供了包括存储单元的半导体器件。 存储单元包括晶体管和电容器，以及电阻器和二极管之一。 晶体管的栅极电连接到字线，并且晶体管的源极和漏极中的一个电连接到位线。 电容器的一个端子电连接到晶体管的源极和漏极中的另一个，并且电容器的另一个端子电连接到布线。 电阻器和二极管中的一个的一个端子电连接到晶体管的源极和漏极中的另一个，并且电阻器和二极管中的一个的另一个端子电连接到布线。
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公开(公告)号：US08199551B2
公开(公告)日：2012-06-12
申请号：US12570619
申请日：2009-09-30
申请人： Takanori Matsuzaki
发明人： Takanori Matsuzaki
IPC分类号： G11C5/06
CPC分类号： H01L27/108 , G11C11/4023 , H01L27/10894
摘要： A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is electrically connected to a bit line. One terminal of the capacitor is electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor is electrically connected to a wiring. One terminal of one of the resistor and the diode is electrically connected to the other of the source and the drain of the transistor, and the other terminal of one of the resistor and the diode is electrically connected to the wiring.
摘要翻译： 提供了包括存储单元的半导体器件。 存储单元包括晶体管和电容器，以及电阻器和二极管之一。 晶体管的栅极电连接到字线，并且晶体管的源极和漏极中的一个电连接到位线。 电容器的一个端子电连接到晶体管的源极和漏极中的另一个，并且电容器的另一个端子电连接到布线。 电阻器和二极管中的一个的一个端子电连接到晶体管的源极和漏极中的另一个，并且电阻器和二极管中的一个的另一个端子电连接到布线。
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公开(公告)号：US20120063205A1
公开(公告)日：2012-03-15
申请号：US13230093
申请日：2011-09-12
IPC分类号： G11C11/24
CPC分类号： H01L27/1052 , G11C8/08 , G11C11/403 , G11C11/405 , G11C11/4085 , G11C16/02 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C2211/4016
摘要： A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.
摘要翻译： 即使在不提供电力的情况下也可以保存存储的数据，并且没有限制写入操作的数量的半导体装置。 使用可以充分降低诸如作为宽间隙半导体的氧化物半导体材料的晶体管的截止电流的材料形成半导体器件。 当使用可以充分降低晶体管的截止电流的半导体材料时，半导体器件可以长期保存数据。 此外，通过提供电连接到写字线的电容器或噪声去除电路，可以减少或去除诸如短脉冲或输入到存储器单元的噪声的信号。 因此，可以防止当存储单元中的晶体管瞬间导通时擦除写入存储单元的数据的故障。
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公开(公告)号：US20120056647A1
公开(公告)日：2012-03-08
申请号：US13221947
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： G11C11/403 , G11C16/0433 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.
摘要翻译： 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。
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公开(公告)号：US20120033485A1
公开(公告)日：2012-02-09
申请号：US13193966
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C11/4076 , G11C11/4087 , H01L27/11521 , H01L27/1156 , H01L27/1207
摘要： In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.
摘要翻译： 在包括位线的m（m为3以上的自然数）字线，源极线，m条信号线，第1〜第m存储器单元和驱动电路的半导体器件中，所述存储单元包括 第一晶体管和第二晶体管，用于存储积聚在电容器中的电荷，第二晶体管包括形成在氧化物半导体层中的沟道。 在半导体装置中，驱动电路使用要输出到第j信号的信号，生成输出到第（j-1）（j为3以上的自然数）信号线的信号 线。
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公开(公告)号：US20120033484A1
公开(公告)日：2012-02-09
申请号：US13193756
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C16/02
摘要： The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.
摘要翻译： 使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。 当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以长时间保存数据。 此外，信号线中的电位变化的定时相对于写入字线的电位变化的定时被延迟。 这使得可以防止数据写入错误。
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公开(公告)号：US20110280061A1
公开(公告)日：2011-11-17
申请号：US13094863
申请日：2011-04-27
CPC分类号： H01L29/78 , G11C11/403 , G11C11/406 , G11C16/0416 , G11C2211/4065 , H01L27/11521 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.
摘要翻译： 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。
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