公开(公告)号：US06975033B2

公开(公告)日：2005-12-13

申请号：US10247378

申请日：2002-09-20

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Takashi Kawanoue

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Takashi Kawanoue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.

摘要翻译： 半导体器件包括其上形成有元件的半导体衬底，形成在半导体衬底上并具有3或更低的相对介电常数的低介电常数绝缘膜，埋入低介电常数绝缘膜中的插塞和布线层 以及杨氏模量为15GPa以上的高杨氏模量绝缘膜，并且与低介电常数绝缘膜和插塞之间的插塞侧接触形成。

公开(公告)号：US06229211B1

公开(公告)日：2001-05-08

申请号：US09362683

申请日：1999-07-29

申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.

摘要翻译： 半导体器件包括基底层，形成在基底层上的阻挡金属层和形成在阻挡金属层上的金属互连，阻挡金属层由选自金属元素和至少一个元素β的至少一种元素α制成 选自一组硼，氧，碳和氮，并且具有至少两个具有原子级别的不同组成比的英文字母复合膜，以形成层压体。 当复合薄膜字母表中包含的元素α相同且相同时，至少两个化合物薄膜字母表中的至少一个是化合物薄膜字母（x> 1）时，器件的通孔电阻和互连电阻可以减小 同时保持高屏障效果。

公开(公告)号：US5498909A

公开(公告)日：1996-03-12

申请号：US937398

申请日：1992-08-31

申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuhito Sawabe ,  Takashi Kawanoue ,  Yoshiko Kohanawa ,  Shuichi Komatsu

发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuhito Sawabe ,  Takashi Kawanoue ,  Yoshiko Kohanawa ,  Shuichi Komatsu

IPC分类号： C30B25/14 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/532 ,  H01L27/04 ,  H01L29/41 ,  H01L23/48 ,  H01L23/28 ,  H01L29/40

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002

摘要： The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.

摘要翻译： 形成电极线的单晶的紧密平面平行于线的纵向方向布置，其中活性区域尺寸减小，即高度集成的半导体器件的电极或线路的电极线， 或者在多晶电极线的情况下，将其晶粒的紧密接合面的法线方向与电极线的法线方向之间形成的角度设定为80°以下。

公开(公告)号：US06001461A

公开(公告)日：1999-12-14

申请号：US771388

申请日：1996-12-19

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L23/532 ,  H01L21/32051 ,  H01L23/5283 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/2457 ,  Y10T428/24926

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US5709958A

公开(公告)日：1998-01-20

申请号：US451528

申请日：1995-05-26

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L29/43

CPC分类号： H01L21/32051 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/12528 ,  Y10T428/12674 ,  Y10T428/12681

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US5187561A

公开(公告)日：1993-02-16

申请号：US545870

申请日：1990-06-29

申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuhito Sawabe ,  Takashi Kawanoue ,  Yoshiko Kohanawa ,  Shuichi Komatsu

发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuhito Sawabe ,  Takashi Kawanoue ,  Yoshiko Kohanawa ,  Shuichi Komatsu

IPC分类号： C30B25/14 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L23/532 ,  H01L27/04 ,  H01L29/41

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002

摘要： The close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80.degree. or less.

公开(公告)号：US20060060977A1

公开(公告)日：2006-03-23

申请号：US11231749

申请日：2005-09-22

申请人： Takashi Kawanoue

发明人： Takashi Kawanoue

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a low dielectric constant insulating layer formed above a semiconductor substrate having an element region, and a Cu wiring isolated by the low dielectric constant insulating layer. Between the low dielectric constant insulating layer and the Cu wiring, there is disposed an ionization suppressing layer containing an element with a work function of less than 3 eV as a simple substance, a Cu concentration of the ionization suppressing layer being less than 10 atomic percent.

摘要翻译： 半导体器件包括在具有元件区域的半导体衬底之上形成的低介电常数绝缘层和由低介电常数绝缘层隔离的Cu布线。 在低介电常数绝缘层和Cu布线之间，设置含有功函数小于3eV的元素作为单质的电离抑制层，电离抑制层的Cu浓度小于10原子％ 。

公开(公告)号：US06518177B1

公开(公告)日：2003-02-11

申请号：US09783561

申请日：2001-02-15

申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

摘要翻译： 通过由选自金属元素的至少一种元素α和在含氧（O）的基底层上选自硼，碳和氮的至少一种元素γ制成的化合物膜，形成半导体器件，以及 通过使化合物膜alphagammax减少基底层从而氧化化合物膜的碱性和底层的界面上的化合物膜，形成化合物膜alphagammayOz，其中x和y分别为原子数 元素γ与元素α的原子数之比，z是氧原子数与元素α原子数之比。

公开(公告)号：US06348402B1

公开(公告)日：2002-02-19

申请号：US09526880

申请日：2000-03-16

申请人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

发明人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer. Thereby, a thin second metal oxide layer having excellent barrier properties against an interconnection material and excellent adhesion to the interconnection material can be selectively formed with a uniform thickness on the surface of the first conductive layer used as a barrier metal layer of the interconnection.

摘要翻译： 在形成于半导体衬底上的绝缘层中形成沟槽，在绝缘层的表面上形成包括第一金属元件的第一导电层。 通过氧化第一导电层，在第一导电层的表面上形成第一金属元素的氧化物层。 在其上沉积包括具有低于第一金属元素的自由能的氧化物形成的第二金属元素的第二导电层。 通过由第二金属元件还原第一金属元件的氧化物层，在第一导电层和第二导电层之间的界面处形成第二金属元素的氧化物层。 此外，互连被埋在绝缘层的凹槽或孔中。 由此，可以在用作互连的阻挡金属层的第一导电层的表面上选择性地形成具有优良的互连材料阻隔性和对互连材料的优异粘附性的薄的第二金属氧化物层。