公开(公告)号：US08975742B2

公开(公告)日：2015-03-10

申请号：US13598751

申请日：2012-08-30

申请人： Toshiki Furutani ,  Takeshi Furusawa

发明人： Toshiki Furutani ,  Takeshi Furusawa

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49541 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.

摘要翻译： 印刷布线板包括基板，形成在基板的第一表面上并且包括最外面的导电层的第一累积物和形成在基板的第二表面上并且包括最外面导电层的第二累积层。 第一堆积的最外层具有定位成连接半导体部件的焊盘，第一堆积具有直接在部件下方的部件安装区域，使得第一堆积物的最外层具有该区域中的一部分，第二部分的最外层 积聚部分具有直接在该区域下方的部分，并且这些部分满足在1.1至1.35范围内的比率，其中通过将第二聚集部分的平面面积除以该部分的平面面积获得的比例 第一次积累

公开(公告)号：US08963291B2

公开(公告)日：2015-02-24

申请号：US13112738

申请日：2011-05-20

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US08097948B2

公开(公告)日：2012-01-17

申请号：US12880520

申请日：2010-09-13

申请人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

发明人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。

公开(公告)号：US20110266679A1

公开(公告)日：2011-11-03

申请号：US13095735

申请日：2011-04-27

申请人： Katsuhiko Hotta ,  Takeshi Furusawa ,  Toshikazu Matsui ,  Takuro Homma

发明人： Katsuhiko Hotta ,  Takeshi Furusawa ,  Toshikazu Matsui ,  Takuro Homma

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.

摘要翻译： 提供了一种能够提高半导体器件的半导体器件的可靠性的技术，该半导体器件具有在半导体衬底的主表面上形成的狭缝，以便围绕每个元件形成区域。 在该技术中，第二钝化膜覆盖开口的侧表面，使得用于接合焊盘的第六层互连M6的上表面裸露，并且狭缝的内壁（侧表面和底表面） 围绕保护环的周围并制成第一钝化膜，用于接合的绝缘膜和层间电介质，以使其底部不穿透阻挡绝缘膜。

公开(公告)号：US08018030B2

公开(公告)日：2011-09-13

申请号：US12410170

申请日：2009-03-24

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US07960279B2

公开(公告)日：2011-06-14

申请号：US12493347

申请日：2009-06-29

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

摘要翻译： 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20090242255A1

公开(公告)日：2009-10-01

申请号：US12369115

申请日：2009-02-11

申请人： Hirotaka TANIGUCHI ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

发明人： Hirotaka TANIGUCHI ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

IPC分类号： H05K1/16 ,  H01R43/00

CPC分类号： H05K1/187 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/205 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacturing a wiring board with a built-in electronic component includes providing a first base material comprising a support body and a first metal foil detachably adhered on the support body, forming a connection terminal for mounting an electronic component on the first metal foil of the first base material by an additive method, electrically connecting an electronic component and the connection terminal by arranging the electronic component on the first base material such that a surface of the electronic component on which a circuit is formed faces a surface on which the connection terminal is formed, covering the electronic component with an insulative material after the mounting, and detaching the support body and the first metal foil.

摘要翻译： 制造具有内置电子部件的布线基板的方法包括：提供包括支撑体的第一基材和可拆卸地粘附在所述支撑体上的第一金属箔，形成用于将电子部件安装在所述第一金属箔上的连接端子 的第一基材的第一基材的表面，通过将电子部件布置在第一基材上，使得电子部件的形成有电路的表面面对连接到第一基材的表面， 端子形成，在安装之后用绝缘材料覆盖电子部件，并且分离支撑体和第一金属箔。

公开(公告)号：US20070114668A1

公开(公告)日：2007-05-24

申请号：US11561629

申请日：2006-11-20

申请人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

发明人： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00015

摘要： A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.

摘要翻译： 半导体器件配备有半导体芯片，该半导体芯片具有形成在基板上的至少一层第一绝缘膜，以及布置在高于第一绝缘膜的层上的多个焊盘。 半导体芯片上的多个焊盘平行于半导体芯片的预定的芯片边缘布置。 第一绝缘膜在多个焊盘中的每一个下方的区域中具有加强图案。 在每个垫下面的区域中，第一绝缘膜中的加强图案的占用在每个垫下面的区域允许的预定范围内，并且在加强图案布置在一排中的整个区域中的加强图案的占用 在垂直于预定芯片边缘的方向上的线在高于在与芯片边缘平行的方向上排列成一列的行的整个区域中的加强图案的占有率高。

公开(公告)号：US06479380B2

公开(公告)日：2002-11-12

申请号：US09863348

申请日：2001-05-24

申请人： Takeshi Furusawa ,  Takao Kumihashi ,  Shuntaro Machida

发明人： Takeshi Furusawa ,  Takao Kumihashi ,  Shuntaro Machida

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

摘要翻译： 为了提供一种制造半导体器件的方法，通过该方法可以在具有低介电常数的甲基硅氧烷型膜上形成具有高纵横比的沟槽或孔，即使在较低的情况下也不会导致通孔连接故障或短路故障 层间互连覆盖有蚀刻阻挡层。 该方法包括在甲基硅氧烷型膜的上层上形成具有氧化硅膜的层状膜并使用硬掩模形成层叠膜的工序。 当蚀刻阻挡层被蚀刻时，氧化硅膜用作甲基硅氧烷型膜的硬掩模，并且防止了向甲基硅氧烷型膜的转印。 因此，可以减少多级互连的寄生电容，而不会导致通路连接故障和短路故障。

公开(公告)号：US5609511A

公开(公告)日：1997-03-11

申请号：US421247

申请日：1995-04-13

申请人： Shigeo Moriyama ,  Yoshio Kawamura ,  Yoshio Homma ,  Kikuo Kusukawa ,  Takeshi Furusawa

发明人： Shigeo Moriyama ,  Yoshio Kawamura ,  Yoshio Homma ,  Kikuo Kusukawa ,  Takeshi Furusawa

IPC分类号： B23Q17/24 ,  B24B49/04 ,  B24B49/12 ,  B24D7/12 ,  H01L21/304 ,  B24B49/00 ,  B24B51/00

CPC分类号： B24B37/013 ,  B24B49/12 ,  B24D7/12

摘要： Disclosed is a method of polishing a thin film layer to be polished, which is formed on the surface of a substrate, by pressing the substrate on the surface of a polishing pad and relatively moving the substrate and the polishing pad, the method comprising the steps of: detecting the position of a front surface of the thin film layer to be polished using a first sensor and also detecting the position of a bottom surface of the thin film layer using a second sensor, on the way of the polishing; calculating the residual thickness of the thin film layer on the basis of the detected positions of the front and bottom surfaces of the thin film layer; and controlling the processing condition of the subsequent polishing on the basis of the calculated residual thickness of the thin film layer.

摘要翻译： 本发明公开了一种通过将基板压在抛光垫的表面上并使基板和抛光垫相对移动而形成在基板表面上的抛光薄膜层的方法，该方法包括步骤 使用第一传感器检测待研磨的薄膜层的前表面的位置，并且在抛光的同时使用第二传感器检测薄膜层的底面的位置; 基于检测到的薄膜层的前表面和底表面的位置计算薄膜层的剩余厚度; 并根据计算出的薄膜层的残留厚度来控制后续研磨的处理条件。