公开(公告)号：US20090144688A1

公开(公告)日：2009-06-04

申请号：US11949583

申请日：2007-12-03

申请人： Taku Uchino ,  Alvan Ng

发明人： Taku Uchino ,  Alvan Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use.

摘要翻译： 利用概率方法的互连规划的系统和方法。 一个实施例包括用于在集成电路设计中规划互连模型的方法。 首先定义网络和一组可用于连接每个网络引脚的互连模型。 对于每个网络，评估每个互连模型将用于连接网络引脚的概率。 然后分配集成电路设计中的瓷砖的概率，指示每个互连模型将穿过瓷砖的可能性。 然后，基于分配给集成电路设计中的每个瓦片的概率，生成映射以指示概率路由特性（例如，线路拥塞的概率，互连部件拥塞，功率密度，互连模型使用）。 然后可以将地图输出（例如，打印或以其他方式显示）给用户或存储以备以后使用。

公开(公告)号：US07076405B1

公开(公告)日：2006-07-11

申请号：US09661919

申请日：2000-09-14

申请人： Taku Uchino

发明人： Taku Uchino

IPC分类号： G06G17/10

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of stages. (1) At the outset, output signal waveforms and occurrence probabilities thereof at the first stage of the logic gates are calculated by the use of signal waveforms and occurrence probabilities thereof at primary input terminals of the integrated circuit; (2) next, output signal waveforms and occurrence probabilities thereof at the second stage of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the first stage of the logic gates; and (3) then, output signal waveforms and occurrence probabilities thereof at the n-th stage (n is a natural number) of the logic gates are calculated by the use of the output signal waveform and the occurrence probability thereof at the primary input terminals and the output signal waveform and the occurrence probability thereof at the (n-1)th stage of the logic gates. Thereby, types of the respective elementary waveforms, occurrence probabilities and signal correlations are calculated relating to signals located on each wiring of each stage inside of the integrated circuit and occurring within a predetermined time period.

摘要翻译： 本发明涉及一种用于估计由以多级形式连接的逻辑门组成的集成电路的功耗和噪声电平的方法。 （1）首先，通过在集成电路的主输入端使用信号波形及其发生概率来计算逻辑门的第一级的输出信号波形及其出现概率; （2）接下来，通过使用输出信号波形及其在主输入端的发生概率和输出信号波形及其发生概率来计算逻辑门的第二级的输出信号波形及其发生概率 在逻辑门的第一阶段; 和（3）然后，通过使用输出信号波形及其在主输入端的发生概率来计算逻辑门的第n级（n为自然数）的输出信号波形及其出现概率 以及逻辑门的第n-1级的输出信号波形及其发生概率。 因此，计算与集成电路内部各级的各布线上的信号有关的各种基本波形，发生概率和信号相关的类型，并且在预定时间段内发生。

公开(公告)号：US06272663B1

公开(公告)日：2001-08-07

申请号：US09312828

申请日：1999-05-17

申请人： Taku Uchino

发明人： Taku Uchino

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： A system for reducing undesired radiation generated from an LSI, comprises: a first storage part 2 for storing a circuit connection information for the LSI and a current waveform of an undesired radiation source of the LSI; a transfer function calculating part 6 for calculating a transfer function of undesired radiation, which is transmitted from an undesired radiation source in the LSI to a power source terminal connected to the outside of the LSI, on the basis of the circuit connection information and the current waveform; a second storage part 4 for storing a constraint on an impedance added in the vicinity of the undesired radiation source, and an allowable level of undesired radiation at the power source terminal; and an undesired radiation optimizing part 8 for calculating an impedance, which causes the undesired radiation at the power source terminal to be less than or equal to the allowable level, using the transfer function under the constraint. Thus, undesired radiation generated from the LSI is reduced.

摘要翻译： 一种用于减少从LSI产生的不期望的辐射的系统，包括：第一存储部分2，用于存储LSI的电路连接信息和LSI的不需要的辐射源的电流波形; 传递函数计算部分6，用于根据电路连接信息和电流来计算从LSI中不需要的辐射源发射到连接到LSI外部的电源端子的不需要的辐射的传递函数 波形; 第二存储部分4，用于存储对在不需要的辐射源附近添加的阻抗的约束，以及电源端子处的不期望辐射的允许电平; 以及不期望的辐射优化部分8，用于使用在该约束下的传递函数来计算使电源端子处的不需要的辐射小于或等于允许电平的阻抗。 因此，从LSI产生的不期望的辐射减少。

公开(公告)号：US5966523A

公开(公告)日：1999-10-12

申请号：US782285

申请日：1997-01-13

申请人： Taku Uchino

发明人： Taku Uchino

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5022 ,  G06F2217/10 ,  G06F2217/78

摘要： A method of estimating the power consumption of a semiconductor integrated circuit provides second data for primary inputs of a logic part in the integrated circuit and for nets that determine the signal value of a given net in the logic part. The second data has a multi-terminal Boolean approximation method (MTBAM) data structure. The method prepares first data having the MTBAM data structure from a probability contained in the second data, probabilities calculated according to third data contained in the second data and having a multi-terminal binary decision diagram (MTBDD) data structure, and fourth data generated from the third data and having the MTBDD data structure. According to the first data, the method estimates a probability for the given net. The method prepares such first data for all nets in the integrated circuit, and according to which, estimates the power consumption of the integrated circuit.

摘要翻译： 估计半导体集成电路的功耗的方法为集成电路中的逻辑部分的主要输入提供第二数据，并为确定逻辑部分中给定网络的信号值的网络提供第二数据。 第二个数据具有多终端布尔逼近法（MTBAM）数据结构。 该方法从包含在第二数据中的概率准备具有MTBAM数据结构的第一数据，根据第二数据中包含的第三数据计算出的概率，并具有多端二进制判定图（MTBDD）数据结构，以及从第 第三个数据并具有MTBDD数据结构。 根据第一个数据，该方法估计给定网络的概率。 该方法为集成电路中的所有网络准备这样的第一数据，并据此估计集成电路的功耗。

公开(公告)号：US5847966A

公开(公告)日：1998-12-08

申请号：US616994

申请日：1996-03-14

申请人： Taku Uchino ,  Takashi Mitsuhashi

发明人： Taku Uchino ,  Takashi Mitsuhashi

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06Q50/00 ,  G06Q50/04 ,  G06F17/00

CPC分类号： G06F17/5022 ,  G06F2217/10 ,  G06F2217/78

摘要： A method of estimating power for an integrated circuit based on high speed probability calculation having a high precision with considering correlation between signals may be provided. The method may be performed by calculating probability quantity accompanying to output nodes of respective logical gates, the probability quantity being represented by probability that logical values of the output nodes of respective logical gates are 1 (referred to as "signal probability" hereinafter) and probability that logical values of the output nodes of respective logical gates are changed (referred to as "switching probability" hereinafter), expanding into series a difference P.sub.e -P.sub.a between a strict value P.sub.e of the probability quantity and a value P.sub.a calculated based on supposition that all inputs of respective logical gates are independent, with respect to the probability quantity corresponding to entire input signals of the integrated circuit, and estimating power required for the integrated circuit by first calculating infinite number of terms in the series as a correction term and then employing a value obtained by adding the correction term to the value P.sub.a as an approximate value of the probability quantity.

摘要翻译： 可以提供考虑到信号之间的相关性的基于具有高精度的高速概率计算的集成电路的功率的方法。 该方法可以通过计算伴随各个逻辑门的输出节点的概率来执行，概率量由各个逻辑门的输出节点的逻辑值为1（以下称为“信号概率”）和概率表示的概率 各个逻辑门的输出节点的逻辑值被改变（以下称为“切换概率”），将概率量的严格值Pe与基于假设计算出的值Pa之间的差Pe-Pa串联扩大， 各个逻辑门的所有输入对于与集成电路的整个输入信号相对应的概率量是独立的，并且通过首先计算该系列中的无限数量的项作为校正项，然后采用 通过将校正项加到值Pa上获得的值作为近似值 概率数值。

公开(公告)号：US20110239181A1

公开(公告)日：2011-09-29

申请号：US13045422

申请日：2011-03-10

申请人： Taku UCHINO

发明人： Taku UCHINO

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： In one embodiment, a wiring design method is disclosed. In the wiring design method, schematic wiring is performed on a substrate, and the substrate includes a first wiring layer with first-direction wiring lines and a second wiring layer with second-direction wiring lines; the substrate is divided into a plurality of tiles; the first wiring layer is divided into partial wiring regions with first-direction wiring lines, the second wiring layer is divided into partial wiring regions with second-direction wiring lines, and each partial wiring region corresponds to the tiles; and when the first-direction wiring lines in the tile overflow, the partial wiring region with second-direction wiring lines corresponding to the tile is changed to the partial wiring region with first-direction wiring lines.

摘要翻译： 在一个实施例中，公开了布线设计方法。 在布线设计方法中，在基板上进行原理布线，基板包括具有第一方向布线的第一布线层和具有第二方向布线的第二布线层; 将基板分割为多个瓦片; 第一布线层被分成具有第一方向布线的部分布线区域，第二布线层被分成具有第二方向布线的部分布线区域，并且每个局部布线区域对应于瓦片; 并且当瓦片中的第一方向布线溢出时，与瓦片相对应的具有第二方向布线的部分布线区域被改变为具有第一方向布线的部分布线区域。

公开(公告)号：US07681158B2

公开(公告)日：2010-03-16

申请号：US11733091

申请日：2007-04-09

申请人： Taku Uchino ,  Alvan Ng

发明人： Taku Uchino ,  Alvan Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated with the different timing paths. The required arrival time is a maximum time when associated with forward paths, and a minimum time when associated with backward paths. (S,T) pairs associated with some timing paths are discarded (i.e., the corresponding timing paths are trimmed) to reduce the complexity of the delay budget allocation computations. Remaining (S,T) pairs are used to determine scaling factors for significant timing paths through the edges. The smallest of the scaling factors for each edge can be multiplied by an initial delay associated with the edge to produce a delay budget allocation associated with the edge.

摘要翻译： 确定电路元件延迟预算分配的系统和方法。 一个实施例包括一种方法，包括在集成电路设计中定义定时边缘和对应的定时路径，以及基于所需的到达时间和与不同定时路径相关联的设计松弛（S，T）对来确定每个边缘的延迟预算分配。 所需的到达时间是与正向路径相关联的最大时间，以及与后向路径相关联的最小时间。 （S，T）对被丢弃（即相应的定时路径被修剪）以减少延迟预算分配计算的复杂度。 剩余（S，T）对用于确定通过边缘的重要定时路径的缩放因子。 每个边缘的最小缩放因子可以乘以与边缘相关联的初始延迟，以产生与边缘相关联的延迟预算分配。

公开(公告)号：US20080250371A1

公开(公告)日：2008-10-09

申请号：US11733091

申请日：2007-04-09

申请人： Taku Uchino ,  Alvan Ng

发明人： Taku Uchino ,  Alvan Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Systems and methods for determining delay budget allocations for circuit elements. One embodiment comprises a method including defining timing edges and corresponding timing paths in an integrated circuit design, and determining delay budget allocations for each of the edges based on required arrival time and design slack (S,T) pairs associated with the different timing paths. The required arrival time is a maximum time when associated with forward paths, and a minimum time when associated with backward paths. (S,T) pairs associated with some timing paths are discarded (i.e., the corresponding timing paths are trimmed) to reduce the complexity of the delay budget allocation computations. Remaining (S,T) pairs are used to determine scaling factors for significant timing paths through the edges. The smallest of the scaling factors for each edge can be multiplied by an initial delay associated with the edge to produce a delay budget allocation associated with the edge.

摘要翻译： 确定电路元件延迟预算分配的系统和方法。 一个实施例包括一种方法，包括在集成电路设计中定义定时边缘和对应的定时路径，以及基于所需的到达时间和与不同定时路径相关联的设计松弛（S，T）对来确定每个边缘的延迟预算分配。 所需的到达时间是与正向路径相关联的最大时间，以及与后向路径相关联的最小时间。 （S，T）对被丢弃（即相应的定时路径被修剪）以减少延迟预算分配计算的复杂度。 剩余（S，T）对用于确定通过边缘的重要定时路径的缩放因子。 每个边缘的最小缩放因子可以乘以与边缘相关联的初始延迟，以产生与边缘相关联的延迟预算分配。

公开(公告)号：US08370783B2

公开(公告)日：2013-02-05

申请号：US11949583

申请日：2007-12-03

申请人： Taku Uchino ,  Alvan Ng

发明人： Taku Uchino ,  Alvan Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use.

摘要翻译： 利用概率方法的互连规划的系统和方法。 一个实施例包括用于在集成电路设计中规划互连模型的方法。 首先定义网络和一组可用于连接每个网络引脚的互连模型。 对于每个网络，评估每个互连模型将用于连接网络引脚的概率。 然后分配集成电路设计中的瓷砖的概率，指示每个互连模型将穿过瓷砖的可能性。 然后，基于分配给集成电路设计中的每个瓦片的概率，生成映射以指示概率路由特性（例如，线路拥塞的概率，互连部件拥塞，功率密度，互连模型使用）。 然后可以将地图输出（例如，打印或以其他方式显示）给用户或存储以备以后使用。

公开(公告)号：US20090064068A1

公开(公告)日：2009-03-05

申请号：US11848421

申请日：2007-08-31

申请人： Alvan Wing Ng ,  Taku Uchino

发明人： Alvan Wing Ng ,  Taku Uchino

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/84

摘要： An integrated circuit (IC) floorplan system includes an integration design system that executes IC floorplan software on a semiconductor die IC model. The IC floorplan software includes a timing tool database of the IC model. IC integrators utilize the IC floorplan software to evaluate logic block moves within the IC model. The IC floorplan software analyzes wire interconnect signal propagation time delays that result from prospective logic block moves with the IC model. The IC floorplan software reports back in real time whether or not a prospective move of a logic block from one location to another in the IC model will cause a timing failure due to a wire interconnect time delay exceeding a predetermined timing parameter.

摘要翻译： 集成电路（IC）楼层规划系统包括在半导体管芯IC模型上执行IC楼层平面图软件的集成设计系统。 IC楼层平面图软件包括IC模型的定时工具数据库。 IC集成商利用IC floorplan软件来评估IC模型内的逻辑块移动。 IC楼层平面图软件分析由IC模型预期逻辑块移动导致的有线互连信号传播时间延迟。 IC楼层规划软件实时回报IC模型中逻辑块从一个位置到另一个位置的预期移动是否会由于超过预定定时参数的电线互连时间延迟而导致定时故障。