公开(公告)号：US06828846B2

公开(公告)日：2004-12-07

申请号：US10300807

申请日：2002-11-21

申请人： Takumi Tsukazaki ,  Masato Fukuoka ,  Masanori Kinugasa

发明人： Takumi Tsukazaki ,  Masato Fukuoka ,  Masanori Kinugasa

IPC分类号： H03K1762

CPC分类号： H03K17/6874 ,  H03K17/165 ,  H03K17/6872 ,  H03K2217/0018

摘要： An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.

摘要翻译： 模拟开关电路包括：由第一P沟道MOS晶体管和第一N沟道晶体管构成的模拟开关，其栅极接收控制信号; 比较电路，比较第一输入 - 输出端和第二输入 - 输出端的电位，并向形成第一P沟道MOS晶体管的阱传送更高的电位; 当所述模拟开关处于截止状态时，将形成所述第一P沟道MOS晶体管的阱的电势传送到所述第一P沟道MOS晶体管的栅极的第一潜在输送电路; 基于控制信号操作的第二电位传送电路，以将形成有第一P沟道MOS晶体管的阱的电位传送到第一P沟道MOS晶体管的栅极，以将第一P沟道MOS 晶体管 以及第三电位输送部，其基于所述控制信号进行工作，以导通所述第一P沟道MOS晶体管。

公开(公告)号：US06714051B2

公开(公告)日：2004-03-30

申请号：US10309254

申请日：2002-12-04

申请人： Akira Takiba ,  Masanori Kinugasa ,  Takumi Tsukazaki ,  Toru Fujii ,  Masaru Mizuta

发明人： Akira Takiba ,  Masanori Kinugasa ,  Takumi Tsukazaki ,  Toru Fujii ,  Masaru Mizuta

IPC分类号： H03K190175

CPC分类号： G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： A bus buffer has a controller to generate several control signals; a first terminal via which a first-directional signal is input whereas a second-directional signal is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first internal circuit and a first output buffer; a second-directional signal processor, provided between the second and first terminals, having a second internal circuit and a second output buffer; a first input buffer having a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals; and a second input buffer having a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal, for holding the input to the input buffers at a certain level to decrease a current to pass these circuits, thus achieving low power consumption.

摘要翻译： 总线缓冲器具有控制器以产生若干控制信号; 输入第一方向信号的第一终端，输出第二方向信号; 输出第一方向信号的第二端子，而输入第二方向信号; 设置在第一和第二终端之间的具有第一内部电路和第一输出缓冲器的第一方向信号处理器; 设置在第二和第一终端之间的具有第二内部电路和第二输出缓冲器的第二方向信号处理器; 第一输入缓冲器，具有通过使用至少一个控制信号来去激活第一内部电路和第一输出缓冲器的第一输入保持器; 以及具有第二输入保持器的第二输入缓冲器，用于通过使用所述至少一个控制信号去激活第二内部电路和第二输出缓冲器，以将输入保持在一定电平的输入缓冲器以减小电流以通过这些电路 ，从而实现低功耗。