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6 条记录 (耗时 0.012 秒)

    Post CMP scrubbing of substrates
    1.
    发明申请
    Post CMP scrubbing of substrates 审中-公开
    后CMP底物洗涤

    公开(公告)号：US20050109371A1

    公开(公告)日：2005-05-26

    申请号：US10973827

    申请日：2004-10-26

    申请人： Garrett Sin ,  Terry Ko ,  Sidney Huey

    发明人： Garrett Sin ,  Terry Ko ,  Sidney Huey

    IPC分类号： B08B1/04 ,  B08B3/02 ,  H01L21/00

    CPC分类号： B08B1/002 ,  B08B1/04 ,  B08B3/02 ,  H01L21/67046

    摘要： A cleaning apparatus is provided for brush cleaning a surface of a substrate. The apparatus comprises a first brush having a first surface geometry adapted to scrub a major surface of the substrate, and a second brush having a second surface geometry different from the first surface geometry and adapted to scrub the major surface of the substrate. In one aspect the cleaning apparatus comprises a first scrubbing apparatus having at least one brush with a profiled surface geometry, adapted to scrub a major surface of a substrate, and a second scrubbing apparatus having at least one brush with a smooth surface geometry, adapted to scrub a major surface of a substrate. Numerous other aspects are provided.

    摘要翻译： 提供一种用于刷洗基材表面的清洁装置。 所述装置包括具有适于擦洗所述基底的主表面的第一表面几何形状的第一刷和具有不同于所述第一表面几何形状的第二表面几何形状并适于擦洗所述基底的主表面的第二刷。 在一个方面，清洁设备包括第一洗涤设备，其具有至少一个具有成型表面几何形状的刷子，其适于洗涤基底的主表面;以及第二洗涤设备，其具有至少一个具有光滑表面几何形状的刷子， 擦洗基材的主表面。 提供了许多其他方面。

    Magnetic tunnel junction patterning using Ta/TaN as hard mask
    4.
    发明授权
    Magnetic tunnel junction patterning using Ta/TaN as hard mask 有权
    磁隧道结图案使用Ta / TaN作为硬掩模

    公开(公告)号：US08450119B2

    公开(公告)日：2013-05-28

    申请号：US11378555

    申请日：2006-03-17

    申请人： Chyu-Jiuh Torng ,  Wei Cao ,  Terry Ko

    发明人： Chyu-Jiuh Torng ,  Wei Cao ,  Terry Ko

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/12 ,  H01L43/08

    摘要： An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.

    摘要翻译： 通过使用反应离子蚀刻（RIE）来形成已经形成双层Ta / TaN硬掩模的MTJ叠层来形成MTJ MRAM电池。 硬掩模通过图案化掩模层而形成，该掩模层通过在MTJ堆叠上的Ta层上沉积TaN层而形成。 在堆叠被图案化之后，TaN层起至少两个有利的作用：1）它在保护叠层的过程中保护Ta层免受氧化，2）它用作随后沉积的介电层具有优异粘合性能的表面。

    Magnetic tunnel junction patterning using Ta/TaN as hard mask
    5.
    发明申请
    Magnetic tunnel junction patterning using Ta/TaN as hard mask 有权
    磁隧道结图案使用Ta / TaN作为硬掩模

    公开(公告)号：US20070215911A1

    公开(公告)日：2007-09-20

    申请号：US11378555

    申请日：2006-03-17

    申请人： Chyu-Jiuh Torng ,  Wei Cao ,  Terry Ko

    发明人： Chyu-Jiuh Torng ,  Wei Cao ,  Terry Ko

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/12 ,  H01L43/08

    摘要： An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.

    摘要翻译： 通过使用反应离子蚀刻（RIE）来形成已经形成双层Ta / TaN硬掩模的MTJ叠层来形成MTJ MRAM电池。 硬掩模通过图案化掩模层而形成，该掩模层通过在MTJ堆叠上的Ta层上沉积TaN层而形成。 在堆叠被图案化之后，TaN层起至少两个有利的作用：1）它在保护叠层的过程中保护Ta层免受氧化，2）它用作随后沉积的介电层具有优异粘合性能的表面。

    Selective plasma etching of silicon nitride in presence of silicon or silicon oxides using mixture of NH.sub.3 or SF.sub.6 and HBR and N.sub.2
    6.
    发明授权
    Selective plasma etching of silicon nitride in presence of silicon or silicon oxides using mixture of NH.sub.3 or SF.sub.6 and HBR and N.sub.2 失效
    使用NH3或SF6与HBR和N2的混合物在硅或氧化硅存在下对氮化硅进行选择性等离子体蚀刻

    公开(公告)号：US5877090A

    公开(公告)日：1999-03-02

    申请号：US868061

    申请日：1997-06-03

    申请人： Nallan C. Padmapani ,  Terry Ko

    发明人： Nallan C. Padmapani ,  Terry Ko

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00

    CPC分类号： H01L21/31116

    摘要： An RIE method and apparatus provides uniform and selective etching through silicon nitride material of a supplied workpiece such as a silicon wafer having silicon oxide adjacent to the SiN. A plasma-maintaining gas that includes N.sub.2 having an inflow rate of at least 10 sccm is used to provide etch-depth uniformity across the workpiece. The plasma-maintaining gas further includes HBr and one or both of NF.sub.3 and SF.sub.6.

    摘要翻译： RIE方法和装置通过提供的工件的氮化硅材料提供均匀且选择性的蚀刻，例如具有与SiN相邻的氧化硅的硅晶片。 使用包括具有至少10sccm的流入速率的N 2的等离子体保持气体来提供穿过工件的蚀刻深度均匀性。 等离子体维持气体还包括HBr和NF3和SF6中的一种或两种。