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    Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage
    2.
    发明申请
    Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage 有权
    用于提高半导体器件抗锯齿损伤鲁棒性的裂纹偏转器结构

    公开(公告)号：US20100109128A1

    公开(公告)日：2010-05-06

    申请号：US12613175

    申请日：2009-11-05

    申请人： Jeffrey Alan WEST ,  Thomas D. BONIFIELD ,  Basab CHATTERJEE

    发明人： Jeffrey Alan WEST ,  Thomas D. BONIFIELD ,  Basab CHATTERJEE

    IPC分类号： H01L23/58 ,  H01L21/71

    CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

    摘要翻译： 一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。 裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。 连续金属层不延伸经过连续接触和连续通孔。 连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面 划线或裂纹偏转划痕。

    Planarized selective tungsten metallization system
    5.
    再颁专利
    Planarized selective tungsten metallization system 失效
    平面选择性钨金属化系统

    公开(公告)号：USRE36663E

    公开(公告)日：2000-04-18

    申请号：US473812

    申请日：1995-06-07

    申请人： Gregory C. Smith ,  Thomas D. Bonifield

    发明人： Gregory C. Smith ,  Thomas D. Bonifield

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/00 ,  H01L21/02 ,  H01L21/283 ,  H01L21/90

    CPC分类号： H01L21/32051 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76807

    摘要： In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

    摘要翻译： 在改进的选择钨金属化系统中，将多个孔（20）切割成第一级介电层（18）。 然后在每个孔口（20）中以第二级金属化图案形成第一介电层（18）的外表面上的成核层（52），优选Ti-W合金。 沉积在第一介电层（18）和成核层（52）上的第二介电层（30），并且使用反向第二级金属化图案来蚀刻回到成核层（52）的槽（58）和 进入孔（20）。 此后，通过选择性CVD沉积钨以填充第一级孔（20）和第二级槽（58），直到钨导体（60）的上表面（62）与上表面（38）的上表面（38）基本共面 第二电介质层（30）。

    TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices
    9.
    发明申请
    TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices 审中-公开
    TSVS具有化学暴露的集成电路器件的TSV提示

    公开(公告)号：US20110018107A1

    公开(公告)日：2011-01-27

    申请号：US12899754

    申请日：2010-10-07

    申请人： Thomas D. Bonifield ,  Brian E. Goodlin ,  Mona M. Eissa

    发明人： Thomas D. Bonifield ,  Brian E. Goodlin ,  Mona M. Eissa

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

    摘要翻译： 一种用于制造IC的方法，包括从第一至第
    一通孔（TSV）和IC及其电子组件。 提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。 基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。 在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。 用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。 化学蚀刻通常是三步化学蚀刻。

    TSVS HAVING CHEMICALLY EXPOSED TSV TIPS FOR INTEGRATED CIRCUIT DEVICES
    10.
    发明申请
    TSVS HAVING CHEMICALLY EXPOSED TSV TIPS FOR INTEGRATED CIRCUIT DEVICES 有权
    具有化学电路设备的化学物理TSV

    公开(公告)号：US20090278238A1

    公开(公告)日：2009-11-12

    申请号：US12463282

    申请日：2009-05-08

    申请人： THOMAS D. BONIFIELD ,  BRIAN E. GOODLIN ,  MONA M. EISSA

    发明人： THOMAS D. BONIFIELD ,  BRIAN E. GOODLIN ,  MONA M. EISSA

    IPC分类号： H01L23/52 ,  H01L21/306 ,  H01L21/304

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

    摘要翻译： 一种用于制造IC的方法，包括从第一至第
    一通孔（TSV）和IC及其电子组件。 提供具有包括顶部半导体表面和底部表面的衬底厚度的衬底，其包括至少一个嵌入式TSV，其包括形成在电介质衬垫上的介电衬垫和导电填充材料。 基板的底表面的一部分被机械地移除以接近但不到达嵌入的TSV尖端。 在机械去除之后，具有保护层厚度的保护基层保留在嵌入TSV的尖端上。 用于去除保护基底层的机械蚀刻除外的化学蚀刻用于形成整体的TSV尖端，其具有通常从基底的底表面突出的暴露尖端部分。 化学蚀刻通常是三步化学蚀刻。